Philips Semiconductors Product data sheet
SC28C94Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
19
IPCR – Input Port Change Register
IPCR[7:4] – I/O1b, I/O0b, I/O1a, I/O0a Change-of-State Detectors
These bits are set when a change of state, as defined in the Input
Port section of this data sheet, occurs at the respective pins. They
are cleared when the IPCR is read by the CPU. A read of the IPCR
also clears ISR[7], the input change bit in the interrupt status
register. The setting of these bits can be programmed to generate
an interrupt to the CPU.
IPCR[3:0] – I/O1b, I/O0b, I/O1a, I/O0a State of I/O Pins
These bits provide the current state of the respective inputs. The
information is unlatched and reflects the state of the input pins
during the time the IPCR is read. The IPR is an unlatched register.
Data can change during a read.
ISR – Interrupt Status Register
Important: The setting of these bits and those of the IMR are
essential to the interrupt bidding process.
This register provides the status of all potential interrupt sources.
The contents of this register are masked by the interrupt mask
register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit in
the IMR is also a ‘1’, then the interrupt source represented by this bit
is allowed to enter the interrupt arbitration process. It will generate
an interrupt (the assertion of INTRN low) only if its bid exceeds the
interrupt threshold value. If the corresponding bit in the IMR is a
zero, the state of the bit in the ISR has no effect on the INTRN
output. Note that the IMR does not mask the reading of the ISR; the
complete status is provided regardless of the contents of the IMR.
ISR[7] – I/O Change-of-State
This bit is set when a change-of-state occurs at the I/O1b, I/O0b,
I/O1a, I/O0a input pins. It is reset when the CPU reads the IPCR.
ISR[6] – Channel b Change in Break
This bit, when set, indicates that the receiver has detected the
beginning or the end of a received break. It is reset when the CPU
issues a reset break change interrupt command.
ISR[5] – Receiver Ready or FIFO Full Channel b
Normally the ISR[5] bit being set to one indicates the RxFIFO is
filled with one or more bytes and/or the receiver watch dog timer
(when enabled) has timed out.
The meaning of ISR[5] is controlled by the MR0[6] and MR1[6] bits
which are normally set to 00. The ISR[5] bit setting to one allows
the receiver to present its bid to the arbitration logic. This function is
explained in the “Interrupt Note On 28C94” and under the “Receiver
Interrupt Fill Level”.
ISR[5], if set, will reset when the RxFIFO is read. If the reading of
the FIFO does not reduce the fill level below that determined by the
MR bits, then ISR[5] sets again within two X1 clock times. Further, if
the MR fill level is set at 8 bytes AND there is a byte in the receiver
shift register waiting for an empty FIFO location, then a read of the
RxFIFO will cause ISR[5] to reset. It will immediately set again upon
the transfer of the character in the shift register to the FIFO.
NOTE: The setting of ISR[5] means that the receiver has entered
the bidding process. It is necessary for this bit to set for the receiver
to generate an interrupt. It does not mean it is generating an
interrupt.
ISR[4] – Transmitter Ready Channel b
The function of this bit is programmed by MR0[5:4] (normally set to
00). This bit is set when ever the number of empty TxFIFO
positions exceeds or equals the level programmed in the MR0
register. This condition will almost always exist when the transmitter
is first enabled. It will reset when the empty TxFIFO positions are
reduced to a level less than that programmed in MR0[5:4] or the
transmitter is disabled or reset.
The ISR[4] bit will reset with each write to the TxFIFO. If the write to
the FIFO does not bring the FIFO above the fill level determined by
the MR bits, the ISR[4] bit will set again within two X1 clock times.
NOTE: The setting of ISR[4] means that the transmitter has entered
the bidding process. It is necessary for this bit to set for the
transmitter to generate an interrupt. It does not mean it is
generating an interrupt.
ISR[3] – Counter Ready
In the counter mode of operation, this bit is set when the counter
reaches terminal count and is reset when the counter is stopped by
a stop counter command. It is initialized to ‘0’ when the chip is reset.
In the timer mode, this bit is set once each cycle of the generated
square wave (every other time the C/T reaches zero count). The bit
is reset by a stop counter command. The command, however, does
not stop the C/T.
ISR[2] – Channel a Change in Break
This bit, when set, indicates that the receiver has detected the
beginning or the end of a received break. It is reset when the CPU
issues a reset break change interrupt command.
ISR[1] – Receiver Ready or FIFO Full Channel a
See the description of ISR[5]. The channel ‘a’ receiver operation is
the same as channel ‘b’.
ISR[0] – Transmitter Ready Channel a
See the description of ISR[4]. Channel “a” transmitter operates in
the same manner as channel “b.”
IMR – Interrupt Mask Register
The programming of this register selects which interrupt sources will
be allowed to enter the interrupt arbitration process. This register is
logically ANDED with the interrupt status register. Its function is to
allow the interrupt source it represents to join the bidding process if
the corresponding IMR and ISR bits are both 1. It has no effect on
the value in the ISR. It does not mask the reading of the ISR.
CTUR and CTLR – Counter/Timer Registers
The CTUR and CTLR hold the eight MSBs and eight LSBs,
respectively, of the value to be used by the counter/timer in either
the counter or timer modes of operation. The minimum value which
may be loaded into the CTUR/CTLR registers is H‘0002’. Note that
these registers are write-only and cannot be read by the CPU.
In the timer (programmable divider) mode, the C/T generates a
square wave with a period of twice the value (in clock periods) of
the CTUR and CTLR. If the value in CTUR or CTLR is changed, the
current half-period will not be affected, but subsequent half-periods
will be. The C/T will not be running until it receives an initial ‘Start
Counter’ command (read address at A5–A0 0Eh for C/T ab or read
address 1Eh for C/T cd ). After this, while in timer mode, the C/T will
run continuously. Receipt of a subsequent start counter command
causes the C/T to terminate the current timing cycle and to begin a
new cycle using the values in the CTUR and CTLR.
The counter ready status bit (ISR[3]) is set once each cycle of the
square wave. The bit is reset by a “Stop Counter” command (read
address at A5–A0 0Fh for C/T ab or read address 1Fh for C/T cd).
The command, however, does not stop the C/T. It only resets the
ISR[3] bit; the C/T continues to run. The ISR[3] bit will set again as
the counter passes through 0. The generated square wave is output
on an I/O pin if it is programmed to be the C/T output.
