Philips Semiconductors Product data sheet
SC28C94Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
25
AC ELECTRICAL CHARACTERISTICS
1,
2,
3,
4
V
CC
= 5V ± 10%, T
A
= –40_C to 85_C, unless otherwise specified.
LIMITS
Min Typ Max
Reset timing
t
RES
10 Reset pulse width 200 ns
I/O Port timing
t
PS
11 I/O input setup time before RDN Low 0 ns
t
PH
11 I/O input hold time after RDN High 0 ns
t
PD
11
I/O output valid from
WRN High (WRN or CEN high, whichever occurs first)
RDN Low (RDN or CEN low, whichever occurs last)
40
40
ns
ns
Interrupt timing
t
IR
12
IRQN negated or I/O output High from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (break change interrupt)
Reset command (I/O change interrupt)
Stop C/T command (counter interrupt)
Write IMR (clear of interrupt mask bit)
With respect to a
3.6864MHz clock
on pin X1/CLK
80
80
80
80
80
80
ns
ns
ns
ns
ns
ns
Clock timing
t
CLK
13 X1/CLK low/high time 125/100 ns
t
CLK
13 X1/CLK low/high time (above 4MHz; X1/CLK ÷ 2 active) 56/56 ns
t
CLK
5
13 X1/CLK frequency 0 3.6864 8.0 MHz
t
CTC
13 Counter/timer clock high or low time 60 ns
f
CTC
5
13 Counter/timer clock frequency 0 8 MHz
t
RX
13 RxC high or low time 30 ns
f
RX
5
13
RxC frequency (16X)
RxC frequency (1X)
0
0
16
1.0
MHz
MHz
t
TX
13 TxC high or low time 30 ns
f
TX
5
13
TxC frequency (16X)
TxC frequency (1X)
0
0
16
1.0
MHz
MHz
Transmitter timing
t
TXD
14 TxD output delay from TxC low 70 ns
t
TCS
14 TxC output delay from TxD output data –10 +10 ns
Receiver timing
t
RXS
15 RxD data setup time to RxC high 60 5 ns
t
RXH
15 RxD data hold time from RxC high 60 5 ns
NOTES:
1. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 2.4 V with a transition time of
20 ns maximum. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of V
IL
and V
IH
,
as appropriate.
2. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.
3. Test condition for interrupt and I/O outputs: C
L
= 50 pF, R
L
= 2.7 kΩ to V
CC
. Test conditions for rest of outputs: C
L
= 150 pF.
4. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN
and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
5. The minimum value is not tested, but is guaranteed by design. For t
CLK
minimum test rate is 2.0 MHz.
