PCF8563TS/4,118 Datasheet PCF8563T/5,518, PCF8563TS/4,118, PCF8563TS/5,118 | P16-P18

Product data sheet Rev. 11 — 26 October 2015 16 of 45

NXP Semiconductors

PCF8563

Real-time clock/calendar

8.8 Timer function

The 8-bit countdown timer at address 0Fh is controlled by the Timer_control register at

address 0Eh. The Timer_control register determines one of 4 source clock frequencies for

the timer (4096 Hz, 64 Hz, 1 Hz, or

⁄

Hz), and enables or disables the timer. The timer

counts down from a software-loaded 8-bit binary value. At the end of every countdown,

the timer sets the timer flag TF. The TF may only be cleared by using the interface. The

asserted TF can be used to generate an interrupt on pin INT

. The interrupt may be

generated as a pulsed signal every countdown period or as a permanently active signal

which follows the state of TF. Bit TI_TP is used to control this mode selection. When

reading the timer, the current countdown value is returned.

8.8.1 Register Timer_control

[1] Default value.

[2] These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to

⁄

Hz for power saving.

8.8.2 Register Timer

The register Timer is an 8-bit binary countdown timer. It is enabled and disabled via the

Timer_control register bit TE. The source clock for the timer is also selected by the

Timer_control register. Other timer properties such as interrupt generation are controlled

via the register Control_status_2.

For accurate read back of the count down value, it is recommended to read the register

twice and check for consistent results, since it is not possible to freeze the countdown

timer counter during read back.

Table 23. Timer_control - timer control register (address 0Eh) bit description

Bit Symbol Value Description

7TE 0

[1]

timer is disabled

1 timer is enabled

6 to 2 - - unused

1 to 0 TD[1:0] timer source clock frequency select

[2]

00 4.096 kHz

01 64 Hz

10 1 Hz

[2] 1

⁄

Table 24. Timer - timer value register (address 0Fh) bit description

Bit Symbol Value Description

7 to 0 TIMER[7:0] 00h to FFh countdown period in seconds:

where n is the countdown value

Table 25. Timer register bits value range

Bit

7 6 5 4 3 2 1 0

1286432168421

CountdownPeriod

SourceClockFrequency

---------------------------------------------------------------

Product data sheet Rev. 11 — 26 October 2015 17 of 45

NXP Semiconductors

PCF8563

Real-time clock/calendar

8.9 EXT_CLK test mode

A test mode is available which allows for on-board testing. In such a mode it is possible to

set up test conditions and control the operation of the RTC.

The test mode is entered by setting bit TEST1 in register Control_status_1. Then

pin CLKOUT becomes an input. The test mode replaces the internal 64 Hz signal with the

signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then

generate an increment of one second.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

maximum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is

divided down to 1 Hz by a 2

divide chain called a prescaler. The prescaler can be set into

a known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0 (STOP

must be cleared before the prescaler can operate again).

From a STOP condition, the first 1 second increment will take place after 32 positive

edges on CLKOUT. Thereafter, every 64 positive edges will cause a one-second

increment.

Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.

When entering the test mode, no assumption as to the state of the prescaler can be made.

8.9.1 Operation example:

1. Set EXT_CLK test mode (Control_status_1, bit TEST1 = 1).

2. Set STOP (Control_status_1, bit STOP = 1).

3. Clear STOP (Control_status_1, bit STOP = 0).

4. Set time registers to desired value.

5. Apply 32 clock pulses to CLKOUT.

6. Read time registers to see the first change.

7. Apply 64 clock pulses to CLKOUT.

8. Read time registers to see the second change.

Repeat steps 7 and 8 for additional increments.

Product data sheet Rev. 11 — 26 October 2015 18 of 45

NXP Semiconductors

PCF8563

Real-time clock/calendar

8.10 STOP bit function

The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP

bit function will cause the upper part of the prescaler (F

to F

) to be held in reset and

thus no 1 Hz ticks will be generated (see Figure 10

). The time circuits can then be set and

will not increment until the STOP bit is released (see Figure 11

and Table 26).

The STOP bit function will not affect the output of 32.768 kHz on CLKOUT, but will stop

the generation of 1.024 kHz, 32 Hz, and 1 Hz.

The lower two stages of the prescaler (F

and F

) are not reset; and because the I

C-bus

is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be

between zero and one 8.192 kHz cycle (see Figure 11

Fig 10. STOP bit functional diagram

013aaa089

OSCILLATOR

32768 Hz

16384 Hz

OSCILLATOR STOP

DETECTOR

RESET

2 Hz

1024 Hz

32 Hz

1 Hz tick

STOP

CLKOUT source

reset

8192 Hz

4096 Hz

32768 Hz

1 Hz

Fig 11. STOP bit release timing

001aaf912

8192 Hz

stop released

0 μs to 122 μs

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45

PCF8563TS/4,118

Mfr. #:

Buy PCF8563TS/4,118

Manufacturer:

NXP Semiconductors

Description:

Real Time Clock ULTRA LOW PWR CLOCK RTC IC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

PCF8563TS/4,118

PCF8563TS/4,118

Products related to this Datasheet