PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 11 — 26 October 2015 25 of 45
NXP Semiconductors
PCF8563
Real-time clock/calendar
9.6 Interface watchdog timer
During read/write operations, the time counting circuits are frozen. To prevent a situation
where the accessing device becomes locked and does not clear the interface, the
PCF8563 has a built in watchdog timer. Should the interface be active for more than 1 s
from the time a valid slave address is transmitted, then the PCF8563 will automatically
clear the interface and allow the time counting circuits to continue counting. The watchdog
will trigger between 1 s and 2 s after receiving a valid slave address. Each time the
watchdog period is exceeded, 1 s will be lost from the time counters.
The watchdog is implemented to prevent the excessive loss of time due to interface
access failure e.g. if main power is removed from a battery backed-up system during an
interface access.
a. Correct data transfer: read or write
b. Incorrect data transfer; read or write
Fig 21. Interface watchdog timer
013aaa420
SLAVE ADDRESS
running
time
counters
WD timer
data
WD timer tracking
time counters frozen running
DATA
t < 1 s
DATA
STOP
START
013aaa421
SLAVE ADDRESS
running
time
counters
WD timer
data
WD timer tracking
time counters frozen running
DATA
1 s < t < 2 s
DATA
START
data transfer fail
WD trips
PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 11 — 26 October 2015 26 of 45
NXP Semiconductors
PCF8563
Real-time clock/calendar
10. Internal circuitry
Fig 22. Device diode protection diagram
013aaa348
SDA
V
SS
SCL
INT
CLKOUT
OSCO
V
DD
OSCI
PCF8563
PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 11 — 26 October 2015 27 of 45
NXP Semiconductors
PCF8563
Real-time clock/calendar
11. Limiting values
[1] Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114.
[2] Pass level; Charged-Device Model (CDM), according to Ref. 6 “
JESD22-C101.
[3] Pass level; latch-up testing according to Ref. 7 “
JESD78 at maximum ambient temperature (T
amb(max)
).
[4] According to the NXP store and transport requirements (see Ref. 9 “
UM10569) the devices should be stored at a temperature of +8 C
to +45 C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document.
Table 28. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +6.5 V
I
DD
supply current 50 +50 mA
V
I
input voltage on pins SCL, SDA,
and OSCI
0.5 +6.5 V
V
O
output voltage on pins CLKOUT and INT 0.5 +6.5 V
I
I
input current at any input 10 +10 mA
I
O
output current at any output 10 +10 mA
P
tot
total power dissipation - 300 mW
V
ESD
electrostatic discharge voltage HBM
HVSON10 (PCF8563BS/4)
[1]
- 3500 V
SO8 (PCF8563T/F4)
[1]
TSSOP8 (PCF8563TS/4)
[1]
SO8 (PCF8563T/5)
[1]
-
-
-
-
-
-
2000 V
TSSOP8 (PCF8563TS/5)
[1]
CDM
HVSON10 (PCF8563BS/4)
[2]
2000 V
SO8 (PCF8563T/F4)
[2]
1000 V
SO8 (PCF8563T/5)
[2]
1500 V
TSSOP8 (PCF8563TS/4)
[2]
1500 V
TSSOP8 (PCF8563TS/5)
[2]
1750 V
I
lu
latch-up current
[3]
-200mA
T
stg
storage temperature
[4]
65 +150 C
T
amb
ambient temperature operating device 40 +85 C

PCF8563TS/4,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Real Time Clock ULTRA LOW PWR CLOCK RTC IC
Lifecycle:
New from this manufacturer.
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