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PCF8563TS/4,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 11 — 26 October 2015 22 of 45
NXP Semiconductors
PCF8563
Real-time clock/calendar
9.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I
2
C-bus is illustrated in Figure 16.
Fig 15. System configuration
mba605
MASTER
TRANSMITTER
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER
RECEIVER
SDA
SCL
Fig 16. Acknowledgement on the I
2
C-bus
mbc602
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master
PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 11 — 26 October 2015 23 of 45
NXP Semiconductors
PCF8563
Real-time clock/calendar
9.5 I
2
C-bus protocol
9.5.1 Addressing
Before any data is transmitted on the I
2
C-bus, the device which should respond is
addressed first. The addressing is always carried out with the first byte transmitted after
the start procedure.
The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL
is only an input signal, but the data signal SDA is a bidirectional line.
Two slave addresses are reserved for the PCF8563:
Read: A3h (10100011)
Write: A2h (10100010)
The PCF8563 slave address is illustrated in Figure 17
.
9.5.2 Clock and calendar READ or WRITE cycles
The I
2
C-bus configuration for the different PCF8563 READ and WRITE cycles is shown in
Figure 18
, Figure 19 and Figure 20. The register address is a 4-bit value that defines
which register is to be accessed next. The upper four bits of the register address are not
used.
Fig 17. Slave address
mce189
1 0 1 0 0 0 1 R/W
group 1
group 2
Fig 18. Master transmits to slave receiver (WRITE mode)
S
0ASLAVE ADDRESS REGISTER ADDRESS A ADATA
P
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
R/W
auto increment
memory register address
013aaa346
n bytes
PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 11 — 26 October 2015 24 of 45
NXP Semiconductors
PCF8563
Real-time clock/calendar
(1) At this moment master transmitter becomes master receiver and PCF8563 slave receiver becomes slave transmitter.
Fig 19. Master reads after setting register address (write register address; READ data)
S
0A
SLAVE ADDRESS
REGISTER ADDRESS A A
R/W
A
DATA
013aaa041
P
1
auto increment
memory register address
last byte
R/W
S1
n bytes
(1)
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from master
no acknowledgement
from master
auto increment
memory register address
SLAVE ADDRESS
DATA
Fig 20. Master reads slave immediately after first byte (READ mode)
S
1A
SLAVE ADDRESS DATA
A1DATA
acknowledgement
from slave
acknowledgement
from master
no acknowledgement
from master
R/W
auto increment
register address
013aaa347
auto increment
register address
n bytes last byte
P
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

PCF8563TS/4,118

Mfr. #:
Buy PCF8563TS/4,118
Manufacturer:
NXP Semiconductors
Description:
Real Time Clock ULTRA LOW PWR CLOCK RTC IC
Lifecycle:
New from this manufacturer.
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