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PCF8563TS/4,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 11 — 26 October 2015 19 of 45
NXP Semiconductors
PCF8563
Real-time clock/calendar
[1] F
0
is clocked at 32.768 kHz.
The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP
bit is released. The uncertainty is caused by the prescaler bits F
0
and F
1
not being reset
(see Table 26
) and the unknown state of the 32 kHz clock.
8.11 Reset
The PCF8563 includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I
2
C-bus logic is initialized including the address pointer and
all registers are set according to Table 27
. I
2
C-bus communication is not possible during
reset.
Table 26. First increment of time circuits after STOP bit release
Bit Prescaler bits
[1]
1Hz tick Time Comment
STOP F
0
F
1
-F
2
to F
14
hh:mm:ss
Clock is running normally
0
01-0 0001 1101 0100
12:45:12 prescaler counting normally
STOP bit is activated by user. F
0
F
1
are not reset and values cannot be predicted externally
1
XX-0 0000 0000 0000
12:45:12 prescaler is reset; time circuits are frozen
New time is set by user
1
XX-0 0000 0000 0000
08:00:00 prescaler is reset; time circuits are frozen
STOP bit is released by user
0
XX-0 0000 0000 0000
08:00:00 prescaler is now running
XX-1 0000 0000 0000
08:00:00 -
XX-0 1000 0000 0000
08:00:00 -
XX-1 1000 0000 0000
08:00:00 -
:
::
11-1 1111 1111 1110
08:00:00 -
00-0 0000 0000 0001
08:00:01 0 to 1 transition of F
14
increments the time circuits
10-0 0000 0000 0001
08:00:01 -
:
::
11-1 1111 1111 1111
08:00:01 -
00-0 0000 0000 0000
08:00:01 -
10-0 0000 0000 0000
08:00:01 -
:
::
11-1 1111 1111 1110
08:00:01 -
00-0 0000 0000 0001
08:00:02 0 to 1 transition of F
14
increments the time circuits
013aaa076
0.507813 to 0.507935 s
1.000000 s
PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 11 — 26 October 2015 20 of 45
NXP Semiconductors
PCF8563
Real-time clock/calendar
[1] Registers marked x are undefined at power-up and unchanged by subsequent resets.
8.11.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and hence speed up on-board test of the device. The setting of this
mode requires that the I
2
C-bus pins, SDA and SCL, are toggled in a specific order as
shown in Figure 12
. All timings are required minimums.
Once the override mode has been entered, the device immediately stops, being reset,
and normal operation may commence i.e. entry into the EXT_CLK test mode via I
2
C-bus
access. The override mode may be cleared by writing logic 0 to TESTC. TESTC must be
set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0
during normal operation has no effect except to prevent entry into the POR override
mode.
Table 27. Register reset value
[1]
Address Register name Bit
7 6 5 4 3 2 1 0
00h Control_status_100001000
01h Control_status_200000000
02hVL_seconds 1xxxxxxx
03hMinutes xxxxxxxx
04hHours xxxxxxxx
05hDays xxxxxxxx
06hWeekdays xxxxxxxx
07hCentury_monthsxxxxxxxx
08hYears xxxxxxxx
09hMinute_alarm 1xxxxxxx
0AhHour_alarm 1xxxxxxx
0BhDay_alarm 1xxxxxxx
0ChWeekday_alarm1xxxxxxx
0DhCLKOUT_control1xxxxx00
0EhTimer_control 0xxxxx11
0FhTimer xxxxxxxx
Fig 12. POR override sequence
mgm664
SCL
500 ns 2000 ns
SDA
8 ms
override active
power-on
PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 11 — 26 October 2015 21 of 45
NXP Semiconductors
PCF8563
Real-time clock/calendar
9. Characteristics of the I
2
C-bus
The I
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 13
).
9.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 14
).
9.3 System configuration
A device generating a message is a transmitter; a device receiving a message is a
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves (see Figure 15
).
Fig 13. Bit transfer
mbc621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 14. Definition of START and STOP conditions
mbc622
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

PCF8563TS/4,118

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Buy PCF8563TS/4,118
Manufacturer:
NXP Semiconductors
Description:
Real Time Clock ULTRA LOW PWR CLOCK RTC IC
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New from this manufacturer.
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