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PCF8563TS/4,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 11 — 26 October 2015 31 of 45
NXP Semiconductors
PCF8563
Real-time clock/calendar
[1] C
L
is a calculation of C
trim
and C
OSCO
in series: .
[2] Unspecified for f
CLKOUT
= 32.768 kHz.
[3] All timing values are valid within the operating supply voltage at ambient temperature and referenced to V
IL
and V
IH
with an input voltage
swing of V
SS
to V
DD
.
[4] A detailed description of the I
2
C-bus specification is given in Ref. 11 “UM10204”.
[5] I
2
C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
t
f
fall time of both SDA and SCL signals - - 0.3 s
t
BUF
bus free time between a STOP and START
condition
1.3 - - s
C
b
capacitive load for each bus line - - 400 pF
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - ns
t
SU;STO
set-up time for STOP condition 0.6 - - s
t
w(spike)
spike pulse width on bus - - 50 ns
Table 30. Dynamic characteristics …continued
V
DD
= 1.8 V to 5.5 V; V
SS
=0V; T
amb
=
40
C to +85
C; f
osc
= 32.768 kHz; quartz R
s
=40k
; C
L
= 8 pF; unless otherwise
specified.
Symbol Parameter Conditions Min Typ Max Unit
C
L
C
trim
C
OSCO

C
trim
C
OSCO
+
-----------------------------------------
=
Fig 27. I
2
C-bus timing waveforms
SDA
mga728
SDA
SCL
t
SU;STA
t
SU;STO
t
HD;STA
t
BUF
t
LOW
t
HD;DAT
t
HIGH
t
r
t
f
t
SU;DAT
PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 11 — 26 October 2015 32 of 45
NXP Semiconductors
PCF8563
Real-time clock/calendar
14. Application information
14.1 Quartz frequency adjustment
14.1.1 Method 1: fixed OSCI capacitor
By evaluating the average capacitance necessary for the application layout, a fixed
capacitor can be used. The frequency is best measured via the 32.768 kHz signal
available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz
crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average
5 ppm). Average deviations of 5 minutes per year can be easily achieved.
14.1.2 Method 2: OSCI trimmer
Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a
trimmer is possible.
14.1.3 Method 3: OSCO output
Direct measurement of OSCO out (accounting for test probe capacitance).
Fig 28. Application diagram
mgm665
SCL
SDA
V
SS
OSCI
OSCO
CLOCK CALENDAR
PCF8563
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
V
DD
V
DD
SDA SCL
RR
V
DD
(I
2
C-bus)
R: pull-up resistor
R =
1 F
t
r
C
b
100 nF
PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 11 — 26 October 2015 33 of 45
NXP Semiconductors
PCF8563
Real-time clock/calendar
15. Package outline
Fig 29. Package outline SOT650-1 (HVSON10) of PCF8563BS
0.50.21
0.05
0.00
A
1
E
h
b
UNIT
D
(1)
ye
2
e
1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
3.1
2.9
cD
h
1.75
1.45
y
1
3.1
2.9
2.55
2.15
0.30
0.18
0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT650-1 MO-229 - - -- - -
E
(1)
0.55
0.30
L
0.1
v
0.05
w
0 2 mm1
scale
SOT650-1
HVSON10: plastic thermal enhanced very thin small outline package; no leads;
10 terminals; body 3 x 3 x 0.85 mm
A
(1)
max.
A
A
1
c
detail X
y
D
h
E
h
e
L
10
51
6
D
E
y
1
C
C
B
A
01-01-22
02-02-08
terminal 1
index area
terminal 1
index area
X
e
1
b
AC
C
B
v
M
w
M
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

PCF8563TS/4,118

Mfr. #:
Buy PCF8563TS/4,118
Manufacturer:
NXP Semiconductors
Description:
Real Time Clock ULTRA LOW PWR CLOCK RTC IC
Lifecycle:
New from this manufacturer.
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