PCF8563TS/4,118 Datasheet PCF8563T/5,518, PCF8563TS/4,118, PCF8563TS/5,118 | P7-P9

Product data sheet Rev. 11 — 26 October 2015 7 of 45

NXP Semiconductors

PCF8563

Real-time clock/calendar

8.3 Control registers

8.3.1 Register Control_status_1

[1] Default value.

[2] Bits labeled as N should always be written with logic 0.

8.3.2 Register Control_status_2

Alarm registers

09h Minute_alarm AE_M MINUTE_ALARM (0 to 59)

0Ah Hour_alarm AE_H x HOUR_ALARM (0 to 23)

0Bh Day_alarm AE_D x DAY_ALARM (1 to 31)

0ChWeekday_alarmAE_WxxxxWEEKDAY_ALARM (0 to 6)

CLKOUT control register

0DhCLKOUT_controlFExxxxxFD[1:0]

Timer registers

0EhTimer_controlTExxxxxTD[1:0]

0Fh Timer TIMER[7:0]

Table 4. Formatted registers overview

…continued

Bit positions labelled as x are not relevant. Bit positions labelled with N should always be written with logic 0; if read they

could be either logic 0 or logic 1. After reset, all registers are set according to Table 27.

Address Register name Bit

7 6 5 4 3 2 1 0

Table 5. Control_status_1 - control and status register 1 (address 00h) bit description

Bit Symbol Value Description Reference

7 TEST1 0

[1]

normal mode

must be set to logic 0 during normal operations

Section 8.9

1 EXT_CLK test mode

6N 0

[2]

unused

5STOP0

[1]

RTC source clock runs Section 8.10

1 all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC

clock is stopped (CLKOUT at 32.768 kHz is still available)

4N 0

[2]

unused

3 TESTC 0 Power-On Reset (POR) override facility is disabled; set to logic 0 for

normal operation

Section 8.11.1

[1]

Power-On Reset (POR) override may be enabled

2to0 N 000

[2]

unused

Table 6. Control_status_2 - control and status register 2 (address 01h) bit description

Bit Symbol Value Description Reference

7to5 N 000

[1]

unused

4TI_TP0

[2]

INT is active when TF is active (subject to the status of TIE) Section 8.3.2.1

and

Section 8.8

1INT pulses active according to Table 7 (subject to the status of TIE);

Remark: note that if AF and AIE are active then INT

will be

permanently active

Product data sheet Rev. 11 — 26 October 2015 8 of 45

NXP Semiconductors

PCF8563

Real-time clock/calendar

[1] Bits labeled as N should always be written with logic 0.

[2] Default value.

8.3.2.1 Interrupt output

Bits TF and AF: When an alarm occurs, AF is set to logic 1. Similarly, at the end of a

timer countdown, TF is set to logic 1. These bits maintain their value until overwritten

using the interface. If both timer and alarm interrupts are required in the application, the

source of the interrupt can be determined by reading these bits. To prevent one flag being

overwritten while clearing another, a logic AND is performed during a write access.

Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when

TF or AF is asserted, respectively. The interrupt is the logical OR of these two conditions

when both AIE and TIE are set.

3AF 0

[2]

read: alarm flag inactive Section 8.3.2.1

write: alarm flag is cleared

1 read: alarm flag active

write: alarm flag remains unchanged

2TF 0

[2]

read: timer flag inactive

write: timer flag is cleared

1 read: timer flag active

write: timer flag remains unchanged

1AIE 0

[2]

alarm interrupt disabled

1 alarm interrupt enabled

0TIE 0

[2]

timer interrupt disabled

1 timer interrupt enabled

Table 6. Control_status_2 - control and status register 2 (address 01h) bit description …continued

Bit Symbol Value Description Reference

When bits TIE and AIE are disabled, pin INT will remain high-impedance.

Fig 5. Interrupt scheme

013aaa087

COUNTDOWN COUNTER

AF: ALARM

FLAG

CLEAR

SET

to interface:

read AF

TF: TIMER

CLEAR

SET

PULSE

GENERATOR 2

CLEAR

TRIGGER

TIE

INT

from interface:

clear TF

from interface:

clear AF

set alarm

flag AF

to interface:

read TF

TI_TP

AIE

e.g. AIE

Product data sheet Rev. 11 — 26 October 2015 9 of 45

NXP Semiconductors

PCF8563

Real-time clock/calendar

Countdown timer interrupts: The pulse generator for the countdown timer interrupt uses

an internal clock and is dependent on the selected source clock for the countdown timer

and on the countdown value n. As a consequence, the width of the interrupt pulse varies

(see Table 7

[1] TF and INT become active simultaneously.

[2] n = loaded countdown value. Timer stops when n = 0.

8.4 Time and date registers

The majority of the registers are coded in the BCD format to simplify application use.

8.4.1 Register VL_seconds

[1] Start-up value.

Table 7. INT operation (bit TI_TP = 1)

[1]

Source clock (Hz) INT period (s)

n=1

[2]

n>1

[2]

4096

⁄

8192

⁄

4096

⁄

128

⁄

Table 8. VL_seconds - seconds and clock integrity status register (address 02h) bit

description

Bit Symbol Value Place value Description

7 VL 0 - clock integrity is guaranteed

[1]

- integrity of the clock information is not guaranteed

6 to 4 SECONDS 0 to 5 ten’s place actual seconds coded in BCD format, see Table 9

3 to 0 0 to 9 unit place

Table 9. Seconds coded in BCD format

Seconds value

(decimal)

Upper-digit (ten’s place) Digit (unit place)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00 0000000

01 0000001

02 0000010

: :::::::

09 0001001

10 0010000

: :::::::

58 1011000

59 1011001

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PCF8563TS/4,118

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Real Time Clock ULTRA LOW PWR CLOCK RTC IC

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PCF8563TS/4,118

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