10
FN8211.1
November 11, 2005
Figure 5. D/A Converter Block Diagram
+
-
I1 or I2 Pin
R1 or R2 Pin
R1_External or R2_External
I1DS or I2DS: bits
Vss Vss
I1FSO[1:0]
R1_Low_Current or
R1_Middle_Current or
R1_High_Current or
VRef
Optional external resistor
Select
Circuit
Polarity
Vcc
Voltage
6 or 7 in Control
register 0.
Divider
DAC1 or
DAC2
Input byte
Vss
Vss
or I2FSO[1:0]
bits 1 and 0, or
3 and 2 in Control
register 5
11
10 01
00
R2_High_Current
R2_Middle_Current
R2_Low_Current
Figure 6. Look-up Table (LUT) Operation
DAC 2
8
D0h
D0h
10Fh
8
LUT2
6
LUT2 Row
Out
D1
D0
Select
D2DAS: Bit 7 of
D2DA[7:0] : Control register 4
Selection bits
A
D
D
E
R
8
8
Input Byte
Control register 5
DAC 1
8
90h
90h
CFh
8
LUT1
6
LUT1 Row
Out
D1
D0
Select
D1DAS: Bit 5 of
D1DA[7:0] : Control register 3
Selection bits
A
D
D
E
R
8
8
Input Byte
Control register 5
X9530
11
FN8211.1
November 11, 2005
By examining the block diagram in Figure 5, we see
that the maximum current through pin I1 is set by fixing
values for V(VRef) and R1. The output current can
then be varied by changing the data byte at the D/A
converter input.
In general, the magnitude of the current at the D/A
converter output pins (I1, I2) may be calculated by:
Ix = (V(VRef) / (384 • Rx)) • N
where x = 1,2 and N is the decimal representation of
the input byte to the corresponding D/A converter.
The value for the resistor Rx (x = 1,2) determines the
full scale output current that the D/A converter may
sink or source. The full scale output current has a
maximum value of ±1.6 mA, which is obtained using a
resistance of 510 for Rx. This resistance may be
connected externally to pin Rx of the X9530, or may
be selected from one of three internal values. Bits
I1FSO1 and I1FSO0 select the full scale output
current setting for I1 as described in “I1FSO1 -
I1FSO0: Current Generator 1 Full Scale Output Set
Bits (Non-volatile)” on page 6. Bits I2FSO1 and
I2FSO0 select the maximum current setting for I2 as
described in “I2FSO1–I2FSO0: Current Generator 2
Full Scale Output Current Set Bits (Non-volatile)” on
page 7. When an internal resistor is selected for R1 or
R2, then no resistor should be connected externally at
the corresponding pin.
Bits I1DS and I2DS in Control Register 0 select the
direction of the currents through pins I1 and I2
independently (See “I1DS: Current Generator 1
Direction Select Bit (Non-volatile)” on page 4 and
“Control and Status Register Format” on page 5).
D/A Converter Output Current Response
When the D/A converter input data byte changes by
an arbitrary number of bits, the output current changes
from an intial current level (I
x
) to some final level
(I
x
+ I
x
). The transition is monotonic and glitchless.
D/A Converter Control
The data byte inputs of the D/A converters can be
controlled in three ways:
1) With the A/D converter and through the look-up
tables (default),
2) Bypassing the A/D converter and directly access-
ing the look-up tables,
3) Bypassing both the A/D converter and look-up
tables, and directly setting the D/A converter input
byte.
D1
D0
Select
ADC
AD[5:0]
LUT1 Row
LUT2 Row
Out
D1
D0
Select
Voltage
Voltage Input
Selection bits
Selection bits
Reference
Out
L2DA[5:0]:
Control
Register 2
L1DA[5:0]:
Control
Register 1
L2DAS: bit 6 in
Control register 5
L1DAS: bit 4 in
Control register 5
6
6
Status
Register
Figure 7. Look-Up Table Addressing
X9530
12
FN8211.1
November 11, 2005
The options are summarized in the following tables:
X9530

X9530V14IZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Laser Drivers TEMP COMPENSATION LASER DIODE BIAS CNT
Lifecycle:
New from this manufacturer.
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