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X9530V14IZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
7
FN8211.1
November 11, 2005
I2FSO1–I2FSO0: CURRENT GENERATOR 2 FULL
S
CALE OUTPUT CURRENT SET BITS (NON-VOLATILE)
These two bits are used to set the full scale output
current at the Current Generator 2 pin, I2. If both bits
are set to “0” (default), an external resistor connected
between pin R2 and Vss, determines the full scale
output current available at pin I2. The other three
options are indicated in the table below. The direction
of this current is set by bit I2DS in Control Register 0.
*No external resistor should be connected in these cases between
R2 and V
SS
.
L1DAS: LUT1 DIRECT ACCESS SELECT BIT (NON-
VOLATILE)
When bit L1DAS is set to “0” (default), LUT1 is
addressed by the output of the on-chip A/D converter.
When bit L1DAS is set to “1”, LUT1 is addressed by
bits L1DA5 - L1DA0.
D1DAS: D/A 1 D
IRECT ACCESS SELECT BIT (NON-
VOLATILE)
When bit D1DAS is set to “0” (default), the input to the
D/A converter 1 is a row of LUT1. When bit D1DAS is
set to “1”, that input is the content of the Control
register 3.
L2DAS: LUT2 D
IRECT ACCESS SELECT BIT (NON-
VOLATILE)
When bit L2DAS is set to “0” (default), LUT2 is
addressed by the output of the on-chip A/D converter.
When bit L2DAS is set to “1”, LUT2 is addressed by
bits L2DA5 - L2DA0.
D2DAS: D/A 2 D
IRECT ACCESS SELECT BIT (NON-
VOLATILE)
When bit D2DAS is set to “0” (default), the input to the
D/A converter 2 is a row of LUT2. When bit D2DAS is
set to “1”, that input is the content of the Control
register 4.
Control Register 6
This register is accessed by performing a Read or
Write operation to address 86h of memory.
WEL: W
RITE ENABLE LATCH (VOLATILE)
The WEL bit controls the Write Enable status of the
entire X9530 device. This bit must be set to “1” before
any other Write operation (volatile or nonvolatile).
Otherwise, any proceeding Write operation to memory
is aborted and no ACK is issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the “0”
state (disabled). The WEL bit is enabled by writing
10000000
2
to Control register 6. Once enabled, the
WEL bit remains set to “1” until the X9530 is powered
down, and then up again, or until it is reset to “0” by
writing 00000000
2
to Control register 6.
A Write operation that modifies the value of the WEL
bit will not cause a change in other bits of Control
register 6.
Status Register - ADC Output
This register is accessed by performing a Read
operation to address 87h of memory.
AD5 - AD0: A/D C
ONVERTER OUTPUT BITS (READ
ONLY)
These six bits are the binary output of the on-chip A/D
converter. The output is 000000
2
for minimum input
and 111111
2
for full scale input.
I2FSO1 I2FSO0 I2 Full Scale Output Current
0 0 Set externally via pin R2 (Default)
01 0.4mA*
10 0.85 mA*
11 1.3 mA*
X9530
8
FN8211.1
November 11, 2005
VOLTAGE REFERENCE
The voltage reference to the A/D and D/A converters
on the X9530, may be driven from the on-chip voltage
reference, or from an external source via the VRef pin.
Bit VRM in Control Register 0 selects between the two
options (See Figure 2).
The default value of VRM is “0”, which selects the
internal reference. When the internal reference is
selected, it’s output voltage is also an output at pin
VRef with a nominal value of 1.21 V. If an external
voltage reference is preferred, the VRM bit of the
Control Register 0 must be set to “1”.
Figure 2. Voltage Reference Structure
A/D CONVERTER
The X9530 contains a general purpose, on-chip, 6-bit
Analog to Digital (A/D) converter whose output is
available at the Status Register as bits AD[5:0]. By
default these output bits are used to select a row in the
look-up tables associated with the X9530’s Current
Generators. When bit ADCfiltOff is “0” (default), bits
AD[5:0] are updated each time the ADC performs four
consecutive conversions with the same exact result.
When bit ADCfiltOff is “1”, these bits are updated after
every ADC conversion.
A block diagram of the A/D converter is shown in
Figure 3. The voltage reference input (see “VOLTAGE
REFERENCE” for details), sets the maximum
amplitude of the ramp generator output. The A/D
converter input signal (see “A/D Converter Input
Select” below for details) is compared to the ramp
generator output. The control and encode logic
produces a binary encoded output, with a minimum
value of 00h (0
10
), and a full scale output value of 3Fh
(63
10
).
The A/D converter input voltage range (VIN
ADC
) is
from 0 V to V(VRef).
A/D Converter Input Select
The input signal to the A/D converter on the X9530,
may be the output of the on-chip temperature sensor,
or an external source via the VSense pin. Bit ADCIN in
Control register 0 selects between the two options
(See Figure 4). It’s default value is “0”, which selects
the internal temperature sensor.
If an external source is intended as the input to the
A/D converter, the ADCIN bit of the Control register 0
must be set to “1”.
VRM: bit 2 in Control register 0.
VRef Pin
On-chip
A/D Converter and
Voltage
Reference
D/A Converters reference
Figure 3. A/D Converter Block Diagram
Ramp
Generator
A/D Converter Input
From VRef
Clock
Control and
Encode Logic
Conversion Reset
A/D Converter
Output
(To LUTs
and Status
Register)
6
Comparator
X9530
9
FN8211.1
November 11, 2005
Figure 4. A/D Converter Input Select Structure
A/D Converter Range
From Figure 3 we can see that the operating range of
the A/D converter input depends on the voltage
reference. And from Figure 4 we see that the internal
temperature Sensor output also varies with the voltage
reference (VRef).
The table below summarizes the voltage range
restrictions on the VSense and VRef pins in different
configurations :
VSense and VRef ranges
LOOK-UP TABLES
The X9530 memory array contains two 64-byte look-up
tables. One is associated to pin I1’s output current
generator and the other to pin I2’s output current
generator, through their corresponding D/A converters.
The output of each look-up table is the byte contained in
the selected row. By default these bytes are the inputs
to the D/A converters driving pins I1 and I2.
The byte address of the selected row is obtained by
adding the look-up table base address (90h for LUT1,
and D0h for LUT2) and the appropriate row selection
bits. See Figure 6.
By default the look-up table selection bits are the 6-bit
output of the A/D converter. Alternatively, the A/D
converter can be bypassed and the six row selection
bits are the six LSBs of Control Registers 1 and 2, for
the LUT1 and LUT2 respectively. The selection
between these options is illustrated in Figure 7, and
described in “I2DS: Current Generator 2 Direction Select
Bit (Non-volatile)” on page 6, and “Control Register 2”
on page 6.
CURRENT GENERATOR BLOCK
The Current Generator pins I1 and I2 are outputs of
two independent current mode D/A converters.
D/A Converter Operation
The Block Diagram for each of the D/A converters is
shown in Figure 5.
The input byte of the D/A converter selects a voltage
on the non-inverting input of an operational amplifier.
The output of the amplifier drives the gate of a FET,
whose source is connected to ground via resistor R1.
This node is also fed back to the inverting input of the
amplifier. The drain of the FET is connected to the
output current pin (I1) via a “polarity select” circuit
block.
VRef A/D Converter Input Ranges
Internal Internal Temp. Sensor Not Applicable
Internal VSense Pin 0 V(VSense)
V(VRef)
External VSense Pin 0 V(VRef) 1.3 V
0 V(VSense) 
V(VRef)
External Internal Temp. Sensor Not a Valid Case
All voltages referred to Vss.
VSense
On-chip
To A/D
ADCIN: bit 3 in Control register 0.
Temperature
Sensor
Pin
VRef
Converter
Input
X9530
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X9530V14IZ

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Buy X9530V14IZ
Manufacturer:
Renesas / Intersil
Description:
Laser Drivers TEMP COMPENSATION LASER DIODE BIAS CNT
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