28
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8211.1
November 11, 2005
TIMING DIAGRAMS
Figure 22. Bus Timing
Figure 23. WP
Pin Timing
Figure 24. Non-Volatile Write Cycle Timing
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
AA
t
R
t
HD:WP
SCL
SDA IN
WP
t
SU:WP
Clk 1
START
STOP
SCL
SDA
t
WC
8th bit of last byte
ACK
Stop
Condition
Start Condition
X9530
