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X9530V14IZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
25
FN8211.1
November 11, 2005
D/A CONVERTER CHARACTERISTICS
All typical values are for 25°C ambient temperature and 5 V at pin Vcc. Maximum and minimum specifications are over the
recommended operating conditions. All voltages are referred to the voltage at pin Vss unless otherwise specified. All bits in
control registers are “0” unless otherwise specified. 510, 0.1%, resistor connected between R1 and Vss, and another
between R2 and Vss unless otherwise specified. 400kHz TTL input at SCL unless otherwise specified. SDA pulled to Vcc
through an external 2k resistor unless otherwise specified. 2-wire interface in “standby” (see notes 1 and 2 on page 22),
unless otherwise specified. WP
, A0, A1, and A2 floating unless otherwise specified.
Notes: 1. LSB is defined as divided by the resistance between R1 or R2 to Vss.
2. Offset
DAC
: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is
expressed in LSB.
FSError
DAC
: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It
is expressed in LSB. The Offset
DAC
is subtracted from the measured value before calculating FSError
DAC
.
DNL
DAC
: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in
the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset
and Full Scale Error before calculating DNL
DAC
.
INL
DAC
: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust-
ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
3. These parameters are periodically sampled and not 100% tested.
Symbol Parameter Min Typ Max Unit Test Conditions / Notes
IFS
00
I1 or I2 full scale current, with external
resistor setting
1.56 1.58 1.6 mA DAC input Byte = FFh,
Source or sink mode, V(I1)
and V(I2) are Vcc - 1.2V in
source mode and 1.2V in sink
mode.
See notes 1 and 2.
IFS
01
I1 or I2 full scale current, with internal
low current setting option
0.3 0.4 0.5 mA
IFS
10
I1 or I2 full scale current, with internal
middle current setting option
0.64 0.85 1.06 mA
IFS
11
I1 or I2 full scale current, with internal
high current setting option
11.3 1.6mA
Offset
DAC
I1 or I2 D/A converter offset error 1 1 LSB
FSError
DAC
I1 or I2 D/A converter full scale error -2 2 LSB
DNL
DAC
I1 or I2 D/A converter
Differential Nonlinearity
-0.5 0.5 LSB
INL
DAC
I1 or I2 D/A converter Integral Nonlin-
earity with respect to a straight line
through 0 and the full scale value
-1 1 LSB
VISink I1 or I2 Sink Voltage Compliance 1.2 Vcc V In this range the current at I1
or I2 vary < 1%
VISource I1 or I2 Source Voltage Compliance 0 Vcc-1.2 V In this range the current at I1
or I2 vary < 1%
I
OVER
I1 or I2 overshoot on D/A Converter
data byte transition
0 A DAC input byte changing from
00h to FFh and vice
versa, V(I1) and V(I2) are
Vcc - 1.2V in source mode
and 1.2V in sink mode.
See note 3.
I
UNDER
I1 or I2 undershoot on D/A Converter
data byte transition
0 A
t
rDAC
I1 or I2 rise time on D/A Converter data
byte transition; 10% to 90%
530s
TCO
I1I2
Temperataure coefficient of output
current I1 or I2 when using internal
resistor setting
±200
ppm/
°C
See Figure 5.
Bits I1FSO[1:0] ¦ 00
2
or
Bits I2FSO[1:0] ¦ 002,
VRMbit = “1”
2
3
V(VRef)
255
x
[]
X9530
26
FN8211.1
November 11, 2005
A/D CONVERTER CHARACTERISTICS
All typical values are for 25°C ambient temperature and 5 V at pin Vcc. Maximum and minimum specifications are over the
recommended operating conditions. All voltages are referred to the voltage at pin Vss unless otherwise specified. All bits in control
registers are “0” unless otherwise specified.
510, 0.1%, resistor connected between R1 and Vss, and another between R2 and Vss
unless otherwise specified. 400kHz TTL input at SCL unless otherwise specified. SDA pulled to Vcc through an external 2k resistor
unless otherwise specified. 2-wire interface in “standby” (see notes 1 and 2 on page 22), unless otherwise specified. WP
, A0, A1, and A2
floating unless otherwise specified.
Notes: 1. “LSB” is defined as V(VRef)/63, “Full Scale” is defined as V(VRef).
2. Offset
ADC
: For an ideal converter, the first transition of its transfer curve occurs a above zero. Offset error is the
amount of deviation between the measured first transition point and the ideal point.
FSError
ADC
: For an ideal converter, the last transition of its transfer curve occurs at .Full Scale Error is the amount
of deviation between the measured last transition point and the ideal point,
after subtracting the Offset from the measured curve.
DNL
ADC
: DNL is defined as the difference between the ideal and the measured code transitions for successive A/D code outputs
expressed in LSBs. The measured transfer curve is adjusted for Offset and Fullscale errors before calculating DNL.
INL
ADC
: The deviation of the measured transfer function of an A/D converter from the ideal transfer function. The INL error is also
defined as the sum of the DNL errors starting from code 00h to the code where the INL measurement is desired. The measured trans-
fer curve is adjusted for Offset and Fullscale errors before calculating INL.
3. These parameters are periodically sampled and not 100% tested.
Symbol Parameter Min Typ Max Unit Test Conditions / Notes
ADCTIME A/D converter conversion
time
9 ms Proportional to A/D converter
input voltage. This value is
maximum at full scale input
of A/D converter.
ADCfiltOff = “1”
RIN
ADC
VSense pin input
resistance
100 k VSense as an input,
ADCIN bit = “1”
CIN
ADC
VSense pin input
capacitance
1 7 pF VSense as an input,
ADCIN bit = “1”,
Frequency = 1 MHz
See note 3.
VIN
ADC
VSense input signal range 0 V(VRef) V This is the A/D Converter
Dynamic Range. ADCIN bit = “1”
Offset
ADC
A/D converter offset error -0.25 0.25 LSB See notes 1 and 2
FSError
ADC
A/D converter full scale er-
ror
-1 1 LSB
DNL
ADC
A/D Converter Differential
Nonlinearity
-0.5 0.5 LSB
INL
ADC
A/D converter Integral
Nonlinearity
-0.5 0.5 LSB
TempStep
ADC
Temperature step causing
one step increment of ADC
output
2.1 2.2 2.3 °C
Out25
ADC
ADC output at 25°C 011101
2
3
1
/2 x V(VRef)
255
[]
251
1
/2 x V(VRef)
255
[]
X9530
27
FN8211.1
November 11, 2005
2-WIRE INTERFACE A.C. CHARACTERISTICS
2-WIRE INTERFACE TEST CONDITIONS
NONVOLATILE WRITE CYCLE TIMING
Notes: 1. Cb = total capacitance of one bus line (SDA or SCL) in pF.
2. t
WC
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It
is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
3. The minimum frequency requirement applies between a START and a STOP condition.
4. These parameters are periodically sampled and not 100% tested.
Symbol Parameter Min Typ Max Units Test Conditions / Notes
f
SCL
SCL Clock Frequency 1
(3)
400 kHz See “2-Wire Interface Test
Conditions” (below),
See Figure 22, Figure 23
and Figure 24.
t
IN
(4)
Pulse width Suppression Time at
inputs
50 ns
t
AA
(4)
SCL Low to SDA Data Out Valid 900 ns
t
BUF
(4)
Time the bus free before start of new
transmission
1300 ns
t
LOW
Clock Low Time 1.3 1200
(3)
s
t
HIGH
Clock High Time 0.6 1200
(3)
s
t
SU:STA
Start Condition Setup Time 600 ns
t
HD:STA
Start Condition Hold Time 600 ns
t
SU:DAT
Data In Setup Time 100 ns
t
HD:DAT
Data In Hold Time 0 s
t
SU:STO
Stop Condition Setup Time 600 ns
t
DH
Data Output Hold Time 50 ns
t
R
(4)
SDA and SCL Rise Time 20
+0.1Cb
(1)
300 ns
t
F
(4)
SDA and SCL Fall Time 20
+0.1Cb
(1)
300 ns
t
SU:WP
(4)
WP Setup Time 600 ns
t
HD:WP
(4)
WP Hold Time 600 ns
Cb
(4)
Capacitive load for each bus line 400 pF
Input Pulse Levels 10 % to 90 % of Vcc
Input Rise and Fall Times, between 10% and 90% 10 ns
Input and Output Timing Threshold Level 1.4V
External Load at pin SDA 2.3 k
to Vcc and 100 pF to Vss
Symbol Parameter Min Typ Max Units Test Conditions / Notes
t
WC
(2)
Nonvolatile Write Cycle Time 5 10 ms See Figure 24
X9530
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

X9530V14IZ

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Buy X9530V14IZ
Manufacturer:
Renesas / Intersil
Description:
Laser Drivers TEMP COMPENSATION LASER DIODE BIAS CNT
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