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X9530V14IZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
16
FN8211.1
November 11, 2005
X9530 Memory Map
The X9530 contains a 2176 bit array of mixed volatile
and nonvolatile memory. This array is split up into four
distinct parts, namely: (Refer to Figure 12.)
– General Purpose Memory (GPM)
– Look-up Table 1 (LUT1)
– Look-up Table 2 (LUT2)
– Control and Status Registers
The GPM is all nonvolatile EEPROM, located at
memory addresses 00h to 7Fh.
Figure 12. X9530 Memory Map
The Control and Status registers of the X9530 are
used in the test and setup of the device in a system.
These registers are realized as a combination of both
volatile and nonvolatile memory. These registers
reside in the memory locations 80h through 8Fh. The
reserved bits within registers 80h through 86h, must
be written as “0” if writing to them, and should be
ignored when reading. The reserved registers, from
88h through 8Fh, must not be written, and their
content should be ignored.
Both look-up tables LUT1 and LUT2 are realized as
nonvolatile EEPROM, and extend from memory
locations 90h–CFh and D0h–10Fh respectively. These
look-up tables are dedicated to storing data solely for
the purpose of setting the outputs of Current
Generators I1 and I2 respectively.
All bits in both look-up tables are preprogrammed to
“0” at the factory.
Addressing Protocol Overview
All Serial Interface operations must begin with a
START, followed by a Slave Address Byte. The Slave
address selects the X9530, and specifies if a Read or
Write operation is to be performed.
It should be noted that the Write Enable Latch (WEL)
bit must first be set in order to perform a Write
operation to any other bit. (See “WEL: Write Enable
Latch (Volatile)” on page 7.) Also, all communication to
the X9530 over the 2-wire serial bus is conducted by
sending the MSB of each byte of data first.
Even though the 2176 bit memory consists of four
differing functions, it is physically realized as one
contiguous array, organized as 17 pages of 16 bytes
each.
The X9530 2-wire protocol provides one address byte,
therefore, only 256 bytes can be addressed directly.
The next few sections explain how to access the
different areas for reading and writing.
Figure 13.
Slave Address (SA) Format
SA6SA7
SA5
SA3 SA2
SA1
SA0
Device Type
Identifier
Read or
SA4
Slave Address
Bit(s) Description
SA7 - SA4 Device Type Identifier
SA3 - SA1 Device Address
SA0 Read or Write Operation Select
R/W1010
Address
Device
AS0AS1AS2
Write
X9530
17
FN8211.1
November 11, 2005
Slave Address Byte
Following a START condition, the master must output
a Slave Address Byte (Refer to Figure 13.). This byte
includes three parts:
– The four MSBs (SA7 - SA4) are the Device Type
Identifier, which must always be set to 1010 in order
to select the X9530.
– The next three bits (SA3 - SA1) are the Device
Address bits (AS2 - AS0). To access any part of the
X9530’s memory, the value of bits AS2, AS1, and
AS0 must correspond to the logic levels at pins A2,
A1, and A0 respectively.
– The LSB (SA0) is the R/W
bit. This bit defines the
operation to be performed on the device being
addressed. When the R/W
bit is “1”, then a Read
operation is selected. A “0” selects a Write
operation (Refer to Figure 13.)
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is
correctly issued (including the final STOP condition),
the X9530 initiates an internal high voltage write cycle.
This cycle typically requires 5 ms. During this time,
any Read or Write command is ignored by the X9530.
Write Acknowledge Polling is used to determine
whether a high voltage write cycle is completed.
During acknowledge polling, the master first issues a
START condition followed by a Slave Address Byte.
The Slave Address Byte contains the X9530’s Device
Type Identifier and Device Address. The LSB of the
Slave Address (R/W
) can be set to either 1 or 0 in this
case. If the device is busy within the high voltage
cycle, then no ACK is returned. If the high voltage
cycle is completed, an ACK is returned and the master
can then proceed with a new Read or Write operation.
(Refer to Figure 14.).
Byte Write Operation
In order to perform a Byte Write operation to the
memory array, the Write Enable Latch (WEL) bit of the
Control 6 Register must first be set to “1”. (See “WEL:
Write Enable Latch (Volatile)” on page 7.)
For any Byte Write operation, the X9530 requires the
Slave Address Byte, an Address Byte, and a Data Byte
(See Figure 15). After each of them, the X9530
responds with an ACK. The master then terminates the
transfer by generating a STOP condition. At this time, if
all data bits are volatile, the X9530 is ready for the next
read or write operation. If some bits are nonvolatile, the
X9530 begins the internal write cycle to the nonvolatile
memory. During the internal nonvolatile write cycle, the
X9530 does not respond to any requests from the
master. The SDA output is at high impedance.
A Byte Write operation can access bytes at locations
00h through FEh directly, when setting the Address
Byte to 00h through FEh respectively. Setting the
Address Byte to FFh accesses the byte at location
100h. The other sixteen bytes, at locations FFh and
101h through 10Fh can only be accessed using Page
Write operations. The byte at location FFh can only be
written using a “Page Write” operation.
Writing to Control bytes which are located at byte
addresses 80h through 8Fh is a special case
described in the section “Writing to Control Registers”.
ACK returned?
Issue Slave Address
Byte (Read or Write)
Byte load completed by issuing
STOP. Enter ACK Polling
Issue STOP
Issue START
NO
YES
NO
Continue normal Read or Write
command sequence
PROCEED
YES
complete. Continue command
sequence.
High Voltage
Issue STOP
Figure 14. Acknowledge Polling Sequence
X9530
18
FN8211.1
November 11, 2005
Page Write Operation
The 2176-bit memory array is physically realized as
one contiguous array, organized as 17 pages of 16
bytes each. In order to perform a Page Write operation
to the memory array, the Write Enable Latch (WEL) bit
in Control register 6 must first be set (See “WEL: Write
Enable Latch (Volatile)” on page 7.)
A Page Write operation is initiated in the same manner
as the byte write operation; but instead of terminating
the write cycle after the first data byte is transferred,
the master can transmit up to 16 bytes (See Figure
16). After the receipt of each byte, the X9530
responds with an ACK, and the internal byte address
counter is incremented by one. The page address
remains constant. When the counter reaches the end
of the page, it “rolls over” and goes back to the first
byte of the same page.
For example, if the master writes 12 bytes to a 16-byte
page starting at location 11 (decimal), the first 5 bytes
are written to locations 11 through 15, while the last 7
bytes are written to locations 0 through 6 within that
page. Afterwards, the address counter would point to
location 7. If the master supplies more than 16 bytes of
data, then new data overwrites the previous data, one
byte at a time (See Figure 17).
The master terminates the loading of Data Bytes by
issuing a STOP condition, which initiates the
nonvolatile write cycle. As with the Byte Write
operation, all inputs are disabled until completion of
the internal write cycle.
A Page Write operation cannot be performed on the
page at locations 80h through 8Fh. Next section
describes the special cases within that page.
A Page Write operation starting with byte address
FFh, accesses the page between locations 100h and
10Fh. The first data byte of such operation is written to
location 100h.
Writing to Control Registers
The byte at location 80h, and bytes at locations 85h
through 8Fh are written using Byte Write operations.
They cannot be written using a Page Write operation.
Control bytes 1 through 4, at locations 81h through
84h respectively, are written during a single operation
(See Figure 18). The sequence must be: a START,
followed by a Slave Address byte, with the R/W
bit
equal to “0”, followed by 81h as the Address Byte, and
then followed by exactly four Data Bytes, and a STOP
condition. The first data byte is written to location 81h,
the second to 82h, the third to 83h, and the last one to
84h.
S
t
a
r
t
S
t
o
p
Slave
Address
Address
Byte
Data
Byte
A
C
K
Signals from
the Master
Signals from
the Slave
A
C
K
1
0
100
A
C
K
Write
Signal at SDA
Figure 15. Byte Write Sequence
2 < n < 16
Signals from
the Master
Signals from
the Slave
Signal at SDA
S
t
a
r
t
Slave
Address
Address
Byte
A
C
K
A
C
K
1
0
100
Data Byte (1)
S
t
o
p
A
C
K
A
C
K
Data Byte (n)
Write
Figure 16. Page Write Operation
X9530
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X9530V14IZ

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Buy X9530V14IZ
Manufacturer:
Renesas / Intersil
Description:
Laser Drivers TEMP COMPENSATION LASER DIODE BIAS CNT
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