AD7865ASZ-2REEL Datasheet AD7865ASZ-1, AD7865ASZ-2, AD7865YSZ-1 | P13-P15

REV. B

AD7865

–12–

TIMING AND CONTROL

Reading Between Each Conversion in the Conversion Sequence

Figure 7 shows the timing and control sequence required to

obtain the optimum throughput rate from the AD7865. To

obtain the optimum throughput from the AD7865 the user must

read the result of each conversion as it becomes available. The

timing diagram in Figure 7 shows a read operation each time the

EOC signal goes logic low. The timing in Figure 7 shows a

conversion on all four analog channels (SL1 to SL4 = 1, see

Selecting a Conversion Sequence), hence there are four EOC

pulses and four read operations to access the result of each of

the four conversions.

A conversion is initiated on the rising edge of CONVST. This

places all four track/holds into hold simultaneously. New data

from this conversion sequence is available for the first channel

selected (A

IN1

) 2.4 µs later. The conversion on each subsequent

channel is completed at 2.4 µs intervals. The end of each con-

version is indicated by the falling edge of the EOC signal. The

BUSY output signal indicates the end of conversion for all

selected channels (four in this case).

Data is read from the part via a 14-bit parallel data bus with

standard CS and RD signals. The CS and RD inputs are inter-

nally gated to enable the conversion result onto the data bus.

The data lines DB0 to DB13 leave their high impedance state

when both CS and RD are logic low. Therefore, CS may be

permanently tied logic low and the RD signal used to access the

conversion result. Since each conversion result is latched into its

output data register at the same time EOC goes logic low a

further option would be to tie the EOC and RD pins together

with CS tied logic low and use the rising edge of EOC to latch

the conversion result. Although the AD7865 has some special

features that permit reading during a conversion (e.g., a sepa-

rate supply for the output data drivers, V

DRIVE

), for optimum

performance it is recommended that the read operation be

completed when EOC is logic low, i.e., before the start of the

next conversion. Although Figure 7 shows the read operation

taking place during the EOC pulse, a read operation can take

place at any time. Figure 7 shows a timing specification called

“Quiet Time.” This is the amount of time that should be left

after a read operation and before the next conversion is initi-

ated. The quiet time heavily depends on data bus capacitance

but a figure of 50 ns to 150 ns is typical.

The signal labeled FRSTDATA (First Data Word) indicates to

the user that the pointer associated with the output data regis-

ters is pointing to the first conversion result by going logic high.

The pointer is reset to point to the first data location (i.e., first

conversion result,) at the end of the first conversion just prior to

EOC going low. The pointer is incremented to point to the next

that conversion result is available. If a read takes place before

the next conversion is complete (as shown in Figure 7) then the

pointer is incremented at the end of that conversion when the

EOC pulse goes low. Hence, FRSTDATA in Figure 7 is seen to

go low just after to the second EOC pulse. Repeated read

operations during a conversion will continue to access the data

at the current pointer location until the pointer is incremented

at the end of that conversion. Note: FRSTDATA has an indeter-

minate logic state after initial power-up. This means that for the

first conversion sequence after power-up, the FRSTDATA

logic output may already be logic high before the end of the first

conversion. This condition is indicated by the dashed line in

Figure 7. Also the FRSTDATA logic output may already be

high as a result of the previous read sequence as is the case after

the fourth read in Figure 7. The fourth read (rising edge of RD)

resets the pointer to the first data location. There, however,

FRSTDATA is already high when the next conversion sequence

is initiated.

QUIET

TIME

CONV

BUSY

IN1

IN2

IN3

IN4

100ns

DATA

CONVST

BUSY

EOC

FRSTDATA

H/S SEL

SL1–SL4

ACQ

CONV

Figure 7. Timing Diagram for Reading During Conversion

REV. B

AD7865

–13–

Accessing the Output Data Registers

There are four Output Data Registers, one for each of the four

possible conversion results from a conversion sequence. The

result of the first conversion in a conversion sequence is placed

in Register 1 and the second result is placed in Register 2 and so

on. For example if the conversion sequence V

IN1

, V

IN3

and V

IN4

is selected (see Selecting a Conversion Sequence) the results of

the conversion on V

IN1

, V

IN3

and V

IN4

are placed in Registers 1

to 3 respectively. The Output Data register pointer is reset to

point to Register 1 at the end of the first conversion in the

sequence, just prior to EOC going low. At this point the logic

output FRSTDATA will go logic high to indicate that the out-

put data register pointer is addressing Register 1. When CS and

RD are both logic low the contents of the addressed register are

enabled onto the data bus (DB0–DB13).

DB0 TO

DB13

O/P

DRIVERS

OE #1

NOT VALID

IN3

)

IN1

)

IN4

)

OE #2

OE #3

OE #4

2-BIT

COUNTER

DRIVE

RESET

OUTPUT

DATA REGISTERS

*THE POINTER WILL NOT BE INCREMENTED BY A RISING EDGE ON RD UNTIL

THE CONVERSION RESULT IS IN THE OUTPUT DATA REGISTER. THE POINTER

IS RESET WHEN THE LAST CONVERSION RESULT IS READ

FRSTDATA

POINTER*

AD7865

DECODE

Figure 8. Output Data Registers

When reading the output data registers after a conversion

sequence, i.e., when BUSY goes low, the register pointer is

incremented on the rising edge of the RD signal as shown in

Figure 8. However, when reading the conversion results between

conversions in a conversion sequence the pointer will not be

incremented until a valid conversion result is in the register to

be addressed. In this case the pointer is incremented when the

conversion has ended and the result has been transferred to the

output data register. This happens when EOC goes low, there-

fore EOC may be used to enable the register contents onto the

data bus as described in Reading Between Conversions in the

Conversion Sequence. The pointer is reset to point to Register 1

on the rising edge of the RD signal when the last conversion

result in the sequence is being read. In the example shown in

Figure 8, this means that the pointer is set to Register 1 when

the contents of Register 3 are read.

Reading after the Conversion Sequence

Figure 9 shows the same conversion sequence as Figure 7. In

this case, however, the results of the four conversions (on V

IN1

to V

IN4

) are read after all conversions have finished, i.e., when

BUSY goes logic low. The FRSTDATA signal goes logic high

at the end of the first conversion just prior to EOC going logic

low. As mentioned previously FRSTDATA has an indetermi-

nate state after initial power up, therefore FRSTDATA may

already be logic high. Unlike the case when reading during a

conversion the output data register pointer is incremented on

the rising edge of RD because the next conversion result is avail-

able in this case. This means FRSTDATA will go logic low after

the first rising edge on RD.

Successive read operations will access the remaining conversion

results in ascending channel order. Each read operation incre-

ments the output data register pointer. The read operation that

accesses the last conversion result causes the output data regis-

ter pointer to be reset so that the next read operation will access

the first conversion result again. This is shown in Figure 8 with

the fifth read after BUSY goes low accessing the result of the

conversion on V

IN1

. Thus the output data registers acts as a

circular buffer in which the conversion results may be continu-

ally accessed. The FRSTDATA signal will go high when the

first conversion result is available.

Data is enabled onto the data bus DB0 to DB13 using CS and

RD. Both CS and RD have the same functionality as described

in the previous section. There are no restrictions or performance

implications associated with the position of the read operations

after BUSY goes low, however there is a minimum time between

read operations that must be adhered to. Notice also that a “Quiet

Time” is needed before the start of the next conversion sequence.

QUIET

TIME

DATA

CONVST

BUSY

EOC

FRSTDATA

IN2

IN3

IN1

BUSY

IN1

IN4

Figure 9. Timing Diagram, Reading after the Conversion Sequences

REV. B

AD7865

–14–

Using an External Clock

With the H/S SEL and INT/EXT CLK pins tied to Logic 1, the

AD7865 will expect to be driven from an external clock. The

highest external clock frequency allowed is 5 MHz. This means

a conversion time of 3.2 µs compared to 2.4 µs using the inter-

nal clock. In some instances, however, it may be useful to use an

external clock when high throughput rates are not required. For

example, two or more AD7865s may be synchronized by using

the same external clock for all devices. In this way there is no

latency between output logic signals like EOC due to differences

in the frequency of the internal clock oscillators. Figure 10

shows how the various logic outputs are synchronized to the CLK

signal. The first falling edge of CLKIN must not occur until

200 ns after a conversion has been initiated (rising edge of

CONVST), at which point BUSY will go high. The AD7865

will then convert the analog input signal on the first selected

channel (see Selecting a Conversion Sequence) at a rate deter-

mined by the CLKIN. No external events will occur until the

14th falling edge of CLKIN. The data register output address

is then reset to point to Data Register 1 and FRSTDATA goes

high. This first conversion is complete on the 15th falling edge

of the CLKIN (indicated by EOC going low) and the result

from this conversion is loaded into Data Register 1. EOC goes

high again on the 16th falling edge of CLKIN. Figure 10 shows

a RD pulse occurring when EOC is low, enabling the conversion

result in Data Register 1 onto the data bus. The next 16 pulses

of CLKIN will convert the analog input signal on the second

selected channel and so on until all selected channels have been

converted. BUSY and EOC will go low on the 15th falling edge

of the last conversion sequence and EOC will return high on the

16th falling edge.

Standby Mode Operation

The AD7865 has a Standby Mode whereby the device can be

placed in a low current consumption mode (3 µA typ). The

AD7865 is placed in standby by bringing the logic input STBY

low. The AD7865 can be powered up again for normal opera-

tion by bringing STBY logic high. The output data buffers are

still operational while the AD7865 is in standby. This means the

user can still continue to access the conversion results while the

AD7865 is in standby. This feature can be used to reduce the

average power consumption in a system using low throughput

rates. To reduce the average power consumption the AD7865 can

be placed in standby at the end of each conversion sequence,

i.e., when BUSY goes low and taken out of standby again prior

to the start of the next conversion sequence. The time it takes

the AD7865 to come out of standby is called the “wake-up”

time. This wake-up time will limit the maximum throughput

rate at which the AD7865 can be operated when powering down

between conversions. The AD7865 will wake up in less than

1 µs when using an external reference. When the internal refer-

ence is used, the wake-up time depends on the amount of time

the AD7865 spends in standby mode. For standby times of less

than 10 ms the AD7865 will wake up in less than 5 µs (see Fig-

ure 11). For standby times greater than this some or all of the

charge on the external reference capacitor will have leaked away

and the wake-up time will be dependent on how long it takes to

recharge. For standby times less than one second the wake-up

time will be less than 1 ms. Even if the charge has been completely

depleted the wake-up time will typically be less than 10 ms.

STANDBY TIME – s

2500

5000 7500 10000

2.5

WAKE-UP TIME – s

Figure 11. Wake-Up Time vs. Standby Time Using the On-

Chip Reference

FIRST CONVERSION

COMPLETE

BUSY

EOC

FRSTDATA

CONVST

CLK

23456789101112131415161234567891011121314 115 16 1615

LAST CONVERSION

COMPLETE

Figure 10. Using an External Clock

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

AD7865ASZ-2REEL

Mfr. #:

Buy AD7865ASZ-2REEL

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC Fast Lo-Pwr 4-Ch Simult Sampling 14B

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AD7865ASZ-2REEL

AD7865ASZ-2REEL

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