REV. B
AD7865
–6–
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
1 BUSY Busy Output. The busy output is triggered high by the rising edge of CONVST and remains
high until conversion is completed on all selected channels.
2 FRSTDATA First Data Output. FRSTDATA is a logic output which, when high, indicates that the Output
Data Register Pointer is addressing Register 1See Accessing the Output Data Registers.
3 CONVST Convert Start Input. Logic Input. A low-to-high transition on this input puts all track/holds
into their hold mode and starts conversion on the selected channels. In addition, the state of
the Channel Sequence Selection is also latched on the rising edge of CONVST.
4 CS Chip Select Input. Active low logic input. The device is selected when this input is active.
5 RD Read Input. Active low logic input which is used in conjunction with CS low to enable the
data outputs. Ensure the WR pin is at logic high while performing a read operation.
6 WR Write Input. A rising edge on the WR input, with CS low and RD high, latches the logic state
on DB0 to DB3 into the channel select register.
7 CLK IN/SL1 Conversion Clock Input/Hardware Channel Select. The function of this pin depends upon the
H/S SEL input. When the H/S SEL input is high (choosing software control of the channel
selection sequence), this pin assumes its CLK IN function. CLK IN is an externally applied
clock (that is only necessary when INT/EXT CLK is high) this allows the user to control the
conversion rate of the AD7865. Each conversion needs 16 clock cycles in order for the conver-
sion to be completed. The clock should have a duty cycle that is no greater than 60/40. See
Using an External Clock.
When the H/S SEL input is low (choosing hardware control of the channel conversion se-
quence), this pin assumes its Hardware Channel Select function. The SL1 input determines
whether Channel 1 is included in the channel conversion sequence. The selection is latched
on the rising edge of CONVST. See Selecting a Conversion Sequence.
8 INT/EXT CLK/SL2 Internal/External Clock/Hardware Channel Select. The function of this pin depends upon the
H/S SEL input. When the H/S SEL input is high (choosing software control of the channel
selection sequence), this pin assumes its INT/EXT CLK function. When INT/EXT CLK is at
a Logic 0, the AD7865 uses its internally generated master clock. When INT/EXT CLK is at
Logic 1, the master clock is generated externally to the device and applied to CLK IN.
When the H/S SEL input is low (choosing hardware control of the channel conversion sequence),
this pin assumes its Hardware Channel Select function. The SL2 input determines whether
Channel 2 is included in the channel conversion sequence. The selection is latched on the
rising edge of CONVST. When H/S is at Logic 1 these pins have no function and can be tied
to Logic 1 or Logic 0. See Selecting a Conversion Sequence.
9, 10 SL3, SL4 Hardware Channel Select. When the H/S SEL input is at Logic 0, the SL3 input determines
whether Channel 3 is included in the channel conversion sequence while SL4 determines
whether Channel 4 is included in the channel conversion sequence. When the pin is at Logic
1, the channel is included in the conversion sequence. When the pin is at Logic 0, the channel
is excluded from the conversion sequence. The selection is latched on the rising edge of
CONVST. See Selecting a Conversion Sequence.
11 H/S SEL Hardware/Software Select Input. When this pin is at a Logic 0, the AD7865 conversion
sequence selection is controlled via the SL1SL4 input pins and runs off an internal clock.
When this pin is at Logic 1, the conversion sequence is controlled via the channel select regis-
ter and allows the ADC to run with an internal or external clock. See Selecting a Conversion
Sequence.
12 AGND Analog Ground. General Analog Ground. This AGND pin should be connected to the systems
AGND
plane.
1316 V
IN4x
, V
IN3x
Analog Inputs. See Analog Input section.
17 AGND Analog Ground. Analog Ground reference for the attenuator circuitry. This AGND pin
should be connected to the systems AGND
plane.
1821 V
IN2x
, V
IN1x
Analog Inputs. See Analog Input section.
22 STBY Standby Mode Input. This pin is used to put the device into the power save or standby mode.
The STBY input is high for normal operation and low for standby operation.
23 AGND Analog Ground. General Analog Ground. This AGND pin should be connected to the
systems AGND
plane.
REV. B
AD7865
–7–
Pin Mnemonic Description
24 V
REF
Reference Input/Output. This pin provides access to the internal reference (2.5 V ± 20 mV)
and also allows the internal reference to be overdriven by an external reference source (2.5 V
± 5%). A 0.1 µF decoupling capacitor should be connected between this pin and AGND.
25 AV
DD
Analog Positive Supply Voltage, 5.0 V ± 5%. A 0.1 µF decoupling capacitor should be con-
nected between this pin and AGND.
26 AGND Analog Ground. General Analog Ground. This AGND pin should be connected to the systems
AGND plane.
2734 DB13DB6 Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 6. Three-state TTL outputs.
Output coding is twos complement for AD7865-1 and AD7865-3, and straight binary for
AD7865-2.
35 DV
DD
Positive Supply Voltage for Digital section, 5.0 V ± 5%. A 0.1 µF decoupling capacitor should
be connected between this pin and AGND. Both DV
DD
and AV
DD
should be externally tied
together.
36 V
DRIVE
This pin provides the positive supply voltage for the output drivers (DB0 to DB13), BUSY,
EOC and FRSTDATA. It is normally tied to DV
DD
. V
DRIVE
should be decoupled with a
0.1 µF capacitor. It allows improved performance when reading during the conversion
sequence. Also, the output data drivers may be powered by a 3 V ± 10% supply to facilitate
interfacing to 3 V processors and DSPs.
37 DGND Digital Ground. Ground reference for Digital circuitry. This DGND pin should be connected
to the systems DGND
plane. The systems DGND and AGND planes should be connected
together at one point only, preferably at an AGND pin.
38, 39 DB5, DB4 Data Bit 5 to Data Bit 4. Three-state TTL outputs.
4043 DB3DB0 Data Bit 3 to Data Bit 0. Bidirectional data pins. When a read operation takes place, these
pins are three-state TTL outputs. The channel select register is programmed with the data on
the DB0DB3 pins with standard CS and WR signals. DB0 represents Channel 1 and DB3
represents Channel 4.
44 EOC End-of-Conversion. Active low logic output indicating conversion status. The end of each
conversion in a conversion sequence is indicated by a low going pulse on this line.
REV. B
AD7865
–8–
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 14-bit converter, this is 86.04 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7865 it is defined as:
THD dB
VVVV
V
()
=
++++
20
2
2
3
2
4
2
5
2
6
2
1
log
V
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
and V
5
are the rms amplitudes of the second through the fifth
harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa fb), while the third order
terms include (2 fa + fb), (2 fa fb), (fa + 2 fb) and (fa 2 fb).
The AD7865 is tested using two input frequencies. In this case,
the second and third order terms are of different significance.
The second order terms are usually distanced in frequency from
the original sine waves, while the third order terms are usually at
a frequency close to the input frequencies. As a result, the second
and third order terms are specified separately. The calculation of
the intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual distortion
products to the rms amplitude of the fundamental expressed in dBs.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 10 kHz sine wave signal to one channel and a 50 kHz
signal to another channel and measuring how much of that
signal is coupled onto the first channel. The figure given is the
worst case across all four channels of the AD7865.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Positive Gain Error (AD7865-1, AD7865-3)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal 4 × V
REF
3/2 LSB (AD7865 at
± 10 V), 2 × V
REF
3/2 LSB (AD7865 at ± 5 V range) or
V
REF
3/2 LSB (AD7865 at ± 2.5 V range), after the Bipolar
Offset Error has been adjusted out.
Positive Gain Error (AD7865-2)
This is the deviation of the last code transition (111 . . . 110 to
111 . . . 111) from the ideal 2 × V
REF
3/2 LSB (AD7865 at
0 V to 5 V), V
REF
3/2 LSB (AD7865 at 0 V to 2.5 V) after
the Unipolar Offset Error has been adjusted out.
Unipolar Offset Error (AD7865-2)
This is the deviation of the first code transition (000 . . . 000 to
000 . . . 001) from the ideal AGND + 1/2 LSB.
Bipolar Zero Error (AD7865-1, AD7865-3)
This is the deviation of the midscale transition (all 0s to 1s)
from the ideal AGND 1/2 LSB.
Negative Gain Error (AD7865-1, AD7865-3)
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal 4 × V
REF
+ 1/2 LSB (AD7865 at
± 10 V), 2 × V
REF
+ 1/2 LSB (AD7865 at ± 5 V range) or
V
REF
+ 1/2 LSB (AD7865 at ± 2.5 V range), after Bipolar Zero
Error has been adjusted out.
Track/Hold Acquisition Time
Track/Hold acquisition time is the time required for the out-
put of the track/hold amplifier to reach its final value, within
± 1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where there is a step input change on the input voltage applied
to the selected V
INxA
/V
INxB
input of the AD7865. It means that
the user must wait for the duration of the track/hold acquisition
time after the end of conversion or after a step input change to
V
INxA
/V
INxB
before starting another conversion, to ensure that
the part operates to specification.

AD7865ASZ-2REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Fast Lo-Pwr 4-Ch Simult Sampling 14B
Lifecycle:
New from this manufacturer.
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