XRT86VX38IB329-F Datasheet XRT86VX38IB329-F | P1-P3

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

XRT86VX38

OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

OCTOBER 2013 REV. 1.0.3

GENERAL DESCRIPTION

The XRT86VX38 is an eight-channel 1.544 Mbit/s or

2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Short-

hual LIU integrated solution featuring R

technology

(Relayless, Reconfigurable, Redundancy) and BITS

Timing element. The physical interface is optimized

with internal impedance, and with the patented pad

structure, the XRT86VX38 provides protection from

power failures and hot swapping.

The XRT86VX38 contains an integrated DS1/E1/J1

framer and LIU which provide DS1/E1/J1 framing and

error accumulation in accordance with ANSI/ITU_T

specifications. Each framer has its own framing

synchronizer and transmit-receive slip buffers. The

slip buffers can be independently enabled or disabled

as required and can be configured to frame to the

common DS1/E1/J1 signal formats.

Each Framer block contains its own Transmit and

Receive T1/E1/J1 Framing function. There are 3

Transmit HDLC controllers per channel which

encapsulate contents of the Transmit HDLC buffers

into LAPD Message frames. There are 3 Receive

HDLC controllers per channel which extract the

payload content of Receive LAPD Message frames

from the incoming T1/E1/J1 data stream and write the

contents into the Receive HDLC buffers. Each framer

also contains a Transmit and Overhead Data Input

port, which permits Data Link Terminal Equipment

direct access to the outbound T1/E1/J1 frames.

Likewise, a Receive Overhead output data port

permits Data Link Terminal Equipment direct access

to the Data Link bits of the inbound T1/E1/J1 frames.

The XRT86VX38 fully meets all of the latest T1/E1/J1

specifications: ANSI T1/E1.107-1988, ANSI T1/

E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/

E1.408-1990, AT&T TR 62411 (12-90) TR54016, and

ITU G-703, G.704, G706 and G.733, AT&T Pub.

43801, and ETS 300 011, 300 233, JT G.703, JT

G.704, JT G706, I.431. Extensive test and diagnostic

functions include Loop-backs, Boundary scan,

Pseudo Random bit sequence (PRBS) test pattern

generation, Performance Monitor, Bit Error Rate

(BER) meter, forced error insertion, and LAPD

unchannelized data payload processing according to

ITU-T standard Q.921.

Applications and Features (next page)

IGURE 1. XRT86VX38 8-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO

Performance

Monitor

PRBS

Generator &

Analyser

HDLC/LAPD

Controllers

LIU &

Loopback

Control

DMA

Interface

Signaling &

Alarms

JTAG

ALE_AS

RDY_DTACK

P

Select

A[14:0]

D[7:0]

Microprocessor

Interface

Tx Serial

Clock

Rx Serial

Clock

8kHz sync

OSC

Back Plane

1.544-16.384 Mbit/s

Local PCM

Highway

ST-BUS

2-Frame

Slip Buffer

Elastic Store

Tx Serial

Data In

Tx LIU

Interface

2-Frame

Slip Buffer

Elastic Store

Rx LIU

Interface

Rx Framer

Rx Serial

Data Out

RTIP

RRING

TTIP

TRING

External Data

Link Controller

Tx Overhead In Rx Overhead Out

XRT86VX38

1 of 8-channels

Tx Framer

LLB LB

System (Terminal) Side

Line Side

1:1 Turns Ratio

1:2 Turns Ratio

Memory

Intel/Motorola µP

Configuration , Control &

Status Monitor

RxLOS

TxON

INT

XRT86VX38

OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. 1.0.3

APPLICATIONS

 High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems

 SONET/SDH terminal or Add/Drop multiplexers (ADMs)

 T1/E1/J1 add/drop multiplexers (MUX)

 Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1

 BITS Timing

 Digital Access Cross-connect System (DACs)

 Digital Cross-connect Systems (DCS)

 Frame Relay Switches and Access Devices (FRADS)

 ISDN Primary Rate Interfaces (PRA)

 PBXs and PCM channel bank

 T3 channelized access concentrators and M13 MUX

 Wireless base stations

 ATM equipment with integrated DS1 interfaces

 Multichannel DS1 Test Equipment

 T1/E1/J1 Performance Monitoring

 Voice over packet gateways

 Routers

FEATURES

 Supports Section 13 - Synchronization Interface in ITU G.703 for both Transmit and Receive Paths

 Supports SSM Synchronous Messaging Generation (BOC for T1, National Bits for E1) on the Transmit Path

 Supports SSM Synchronous Messaging Extraction (BOC for T1, National Bits for E1) on the Receive Path

 Supports BITS timing generation on the Transmit Outputs

 Supports BITS timing extraction from NRZ data on the Analog Receive Path

 DS-0 Monitoring on both Transmit and Receive Time Slots

 Supports SSM Synchronization Messaging per ANSI T1.101-1999 and ITU G.704

 Supports a Customized Section 13 - Synchronization Interface in G.703 at 1.544MHz

 Independent, full duplex DS1 Tx and Rx Framer/LIUs

 Each channel has full featured Long-haul/Short-haul LIU

 Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz

asynchronous back plane connections with jitter and wander attenuation

 Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 2-channel

multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus

 Programmable output clocks for Fractional T1/E1/J1

 Supports Channel Associated Signaling (CAS)

 Supports Common Channel Signalling (CCS)

 Supports ISDN Primary Rate Interface (ISDN PRI) signaling

XRT86VX38

REV. 1.0.3 OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

 Extracts and inserts robbed bit signaling (RBS)

 3 Integrated HDLC controllers for transmit and receive, each controller having two 96-byte buffers (buffer 0 /

buffer 1)

 HDLC Controllers Support SS7

 Timeslot assignable HDLC

 V5.1 or V5.2 Interface

 Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface

every 1 second or for a single transmission

 Supports SPRM and NPRM

 Alarm Indication Signal with Customer Installation signature (AIS-CI)

 Remote Alarm Indication with Customer Installation (RAI-CI)

 Gapped Clock interface mode for Transmit and Receive.

 Intel/Motorola and Power PC interfaces for configuration, control and status monitoring

 Parallel search algorithm for fast frame synchronization

 Wide choice of T1 framing structures: SF/D4, ESF, SLC®96, T1DM and N-Frame (non-signaling)

 Direct access to D and E channels for fast transmission of data link information

 Full BERT Controller for generation and detection on system and line side of the chip

 PRBS, QRSS, and Network Loop Code generation and detection

 Seven Independent, simultaneous Loop Code Detectors per Channel

 Programmable Interrupt output pin

 Supports programmed I/O and DMA modes of Read-Write access

 The framer block encodes and decodes the T1/E1/J1 Frame serial data

 Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms

 Detects OOF, LOF, LOS errors and COFA conditions

 Loopbacks: Local (LLB) and Line remote (LB)

 Facilitates Inverse Multiplexing for ATM

 Performance monitor with one second polling

 Boundary scan (IEEE 1149.1) JTAG test port

 Accepts external 8kHz Sync reference

 1.8V Inner Core

 3.3V CMOS operation with 5V tolerant inputs

 256-pin fpBGA and 329-pin fpBGA package with -40C to +85C operation

ORDERING INFORMATION

PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE

XRT86VX38IB329 329 Fine Pitch Ball Grid Array

-40

C to +85C

XRT86VX38IB256 256 Fine Pitch Ball Grid Array

-40

C to +85C

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P61

XRT86VX38IB329-F

Mfr. #:

Buy XRT86VX38IB329-F

Manufacturer:

MaxLinear

Description:

Telecom Interface ICs 8Ch 1.544/2.048Mbps Framer/LIU w/R3 tech

Lifecycle:

New from this manufacturer.

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