XRT86VX38IB329-F Datasheet XRT86VX38IB329-F | P25-P27

XRT86VX38

REV. 1.0.3 OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

RxSig0

RxSig1

RxSig2

RxSig3

RxSig4

RxSig5

RxSig6

RxSig7

B12

C16

D18

U18

W14

V12

O8Receive Serial Signaling Output (RxSIGn):

The exact function of these pins depends on whether or

not the receive framer enables the receive fractional/sig-

naling interface, as described below:

If receive fractional/signaling interface is disabled :

-No function

If receive fractional/signaling interface is enabled -

RxSIGn:

These pins can be used to output robbed-bit signaling

data within an inbound DS1 frame or to output Channel

Associated Signaling (CAS) data within an inbound E1

frame, as described below.

T1 Mode: Signaling data (A,B,C,D) of each channel will

be output on bit 4,5,6,7 of each time slot on the RxSIG pin

if 16-code signaling is used. If 4-code signaling is

selected, signaling data (A,B) of each channel will be out-

put on bit 4, 5 of each time slot on the RxSIG pin. If 2-

code signaling is selected, signaling data (A) of each

channel will be output on bit 4 of each time slot on the

RxSIG pin.

E1 Mode: Signaling data in E1 mode will be output on the

RxSIGn pins on a time-slot-basis as in T1 mode, or it can

be output on time slot 16 only via the RxSIGn output pins.

In the latter case, signaling data (A,B,C,D) of channel 1

and channel 17 will be output on the RxSIGn pin during

time slot 16 of frame 1, signaling data (A,B,C,D) of chan-

nel 2 and channel 18 will be output on the RxSIGn pin

during time slot 16 of frame 2...etc. The CAS multiframe

Alignments bits (0000 bits) and the extra bits/alarm bit

(xyxx) will be output on the RxSIGn pin during time slot 16

of frame 0.

OTE: Receive Fractional/signaling interface can be

enabled by programming to bit 4 - RxFr1544/

RxFr2048 bit from register 0xn122 to ‘1’.

RxSCLK0

RxSCLK1

RxSCLK2

RxSCLK3

RxSCLK4

RxSCLK5

RxSCLK6

RxSCLK7

C11

E14

A18

F17

W18

T14

U11

B10

D12

A15

F12

T15

T11

O8Receive Recovered Line Clock Output (RxSCLKn):

The exact function of these pins depends on whether or

not the receive framer enables the receive fractional/sig-

naling interface, as described below:

If receive fractional/signaling interface is disabled -

-No function

If receive fractional/signaling interface is enabled -

Receive Recovered Line Clock Output (RxSCLKn):

These pins output the recovered T1/E1 line clock

(1.544MHz in T1 mode and 2.048MHz in E1 mode) for

each channel.

OTE: Receive Fractional/Signaling interface can be

enabled by programming to bit 4 - RxFr1544/

RxFr2048 bit from register 0xn122 to ‘1’.

RECEIVE SYSTEM SIDE INTERFACE

SIGNAL NAME

329 PKG

BALL#

256 PKG

BALL #

TYPE

OUTPUT

RIVE (MA)

ESCRIPTION

XRT86VX38

OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. 1.0.3

RECEIVE LINE INTERFACE

SIGNAL NAME

329 PKG

BALL#

256 PKG

BALL #

TYPE

OUTPUT

RIVE (MA)

ESCRIPTION

RTIP0

RTIP1

RTIP2

RTIP3

RTIP4

RTIP5

RTIP6

RTIP7

I-Receive Positive Analog Input (RTIPn):

RTIP is the positive differential input from the line inter-

face. This input pin, along with the RRING input pin, func-

tions as the “Receive DS1/E1 Line Signal” input for the

XRT86VX38 device.

The user is expected to connect this signal and the

RRING input signal to a 1:1 transformer for proper opera-

tion. The center tap of the receive transformer should have

a bypass capacitor of 0.1F to ground (Chip Side) to

improve long haul application receive capabilities.

RRING0

RRING1

RRING2

RRING3

RRING4

RRING5

RRING6

RRING7

I-Receive Negative Analog Input (RRINGn):

RRING is the negative differential input from the line inter-

face. This input pin, along with the RTIP input pin, func-

tions as the “Receive DS1/E1 Line Signal” input for the

XRT86VX38 device.

The user is expected to connect this signal and the RTIP

input signal to a 1:1 transformer for proper operation. The

center tap of the receive transformer should have a

bypass capacitor of 0.1F to ground (Chip Side) to

improve long haul application receive capabilities.

RxLOS0

RxLOS1

RxLOS2

RxLOS3

RxLOS4

RxLOS5

RxLOS6

RxLOS7

B13

D15

E18

U19

U15

V11

C11

F11

D16

P16

P12

R10

O4Receive Loss of Signal Output Indicator (RLOSn):

The XRT86VX38 device will assert this output pin (i.e.,

toggle it “high”) anytime (and for the duration that) the

Receive DS1/E1 Framer or LIU block declares the LOS

defect condition.

Conversely, the XRT86VX38 will "TRI-State" this pin any-

time (and for the duration that) the Receive DS1/E1

Framer or LIU block is NOT declaring the LOS defect con-

dition.

NOTE: Since the XRT86VX38 tri-states this output pin

(anytime the channel is not declaring the LOS

defect condition), the user MUST connect a "pull-

down" resistor (ranging from 1K to 10K) to each

RxLOS output pin, to pull this output pin to the

logic "LOW" condition, whenever the Channel is

NOT declaring the LOS defect condition.

This output pin will toggle “High” (declare LOS) if the

Receive Framer or the Receive LIU block associated with

Channel N determines that an RLOS condition occurs. In

other words, this pin is OR-ed with the LIU RLOS and the

Framer RLOS bit. If either the LIU RLOS or the Framer

RLOS bit associated with channel N pulses high, the cor-

responding RLOS pin of that particular channel will be set

to “High”.

XRT86VX38

REV. 1.0.3 OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

RxTSEL B5 A5 I - Receive Termination Control (RxTSEL):

Upon power up, the receivers are in "High" impedance.

Switching to internal termination can be selected through

the microprocessor interface by programming the appro-

priate channel register. However, to switch control to the

hardware pin, RxTCNTL must be programmed to "1" in the

appropriate global register (0x0FE2). Once control has

been granted to the hardware pin, it must be pulled "High"

to switch to internal termination.

OTE: Internally pulled "Low" with a 50kresistor.

TRANSMIT LINE INTERFACE

SIGNAL NAME

329 PKG

BALL#

256 PKG

BALL #

TYPE DESCRIPTION

TTIP0

TTIP1

TTIP2

TTIP3

TTIP4

TTIP5

TTIP6

TTIP7

O Transmit Positive Analog Output (TTIPn):

TTIP is the positive differential output to the line interface. This out-

put pin, along with the corresponding TRING output pin, function as

the Transmit DS1/E1 output signal drivers for the XRT86VX38

device.

The user is expected to connect this signal and the corresponding

TRING output signal to a 1:2 step up transformer for proper opera-

tion.

This output pin will be tri-stated whenever the user sets the “TxON”

input pin or register bit (0xnF02, bit 3) to “0”.

OTE: This pin should have a series line capacitor of 0.68



F for DC

blocking purposes.

TRING0

TRING1

TRING2

TRING3

TRING4

TRING5

TRING6

TRING7

O Transmit Negative Analog Output (TRINGn):

TRING is the negative differential output to the line interface. This

output pin, along with the corresponding TTIP output pin, function as

the Transmit DS1/E1 output signal drivers for the XRT86VX38

device.

The user is expected to connect this signal and the corresponding

TRING output signal to a 1:2 step up transformer for proper opera-

tion.

OTE: This output pin will be tri-stated whenever the user sets the

“TxON” input pin or register bit (0xnF02, bit 3) to “0”.

RECEIVE LINE INTERFACE

SIGNAL NAME

329 PKG

BALL#

256 PKG

BALL #

TYPE

OUTPUT

RIVE (MA)

ESCRIPTION

RxTSEL (pin) Rx Termination

External

Internal

Note: RxTCNTL (bit) must be set to "1"

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P61

XRT86VX38IB329-F

Mfr. #:

Buy XRT86VX38IB329-F

Manufacturer:

MaxLinear

Description:

Telecom Interface ICs 8Ch 1.544/2.048Mbps Framer/LIU w/R3 tech

Lifecycle:

New from this manufacturer.

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XRT86VX38IB329-F