XRT86VX38
40
REV. 1.0.2 OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
AC ELECTRICAL CHARACTERISTICS TRANSMIT FRAMER (BASE RATE/NON-MUX)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
S
YMBOL PARAMETER MIN.TYP.MAX.UNITS CONDITIONS
t
1
TxSERCLK to TxMSYNC delay 234 nS
t
2
TxSERCLK to TxSYNC delay 230 nS
t
3
TxSERCLK to TxSER data delay 230 nS
t
4
Rising Edge of TxSERCLK to Rising Edge of TxCH-
CLK
13 nS
t
5
TxSERCLK to TxSIG delay 230 nS
FIGURE 2. FRAMER SYSTEM TRANSMIT TIMING DIAGRAM (BASE RATE/NON-MUX)
AC ELECTRICAL CHARACTERISTICS RECEIVE FRAMER (BASE RATE/NON-MUX)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
S
YMBOL PARAMETER MIN.TYP.MAX.UNITS CONDITIONS
RxSERCLK as an Output
t
8
Rising Edge of RxSERCLK to Rising Edge of
RxCASYNC
4nS
t
9
Rising Edge of RxSERCLK to Rising Edge of
RxCRCSYNC
4nS
t
10
Rising Edge of RxSERCLK to Rising Edge of
RxSYNC (RxSYNC as Output)
4nS
t
11
Rising Edge of RxSERCLK to Rising Edge of
RxSER
6nS
RxSERCLK as an Input
TxMSYNC
TxSYNC
TxSERCLK
TxSER
TxCHN_0
(TxSIG)
ABCD
t
1
t
2
t
3
t
5
XRT86VX38
41
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. 1.0.2
t
13
Rising Edge of RxSERCLK to Rising Edge of
RxCASYNC
8nS
t
14
Rising Edge of RxSERCLK to Rising Edge of
RxCRCSYNC
8nS
t
15
Rising Edge of RxSERCLK to Rising Edge of
RxSYNC (RxSYNC as Output)
10 nS
t
15
Rising Edge of RxSERCLK to Rising Edge of
RxSYNC (RxSYNC as Input)
230 nS
t
16
Rising Edge of RxSERCLK to Rising Edge of
RxSER
10 nS
FIGURE 3. FRAMER SYSTEM RECEIVE TIMING DIAGRAM (RXSERCLK AS AN OUTPUT)
F
IGURE 4. FRAMER SYSTEM RECEIVE TIMING DIAGRAM (RXSERCLK AS AN INPUT)
AC ELECTRICAL CHARACTERISTICS RECEIVE FRAMER (BASE RATE/NON-MUX)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
S
YMBOL PARAMETER MIN.TYP.MAX.UNITS CONDITIONS
t
8
t
9
t
10
t
11
RxSER
RxSERCLK
RxSYNC
RxCASYNC
RxCRCSYNC
(Output)
t
13
t
14
t
15
t
16
RxSER
RxSERCLK
RxSYNC
RxCASYNC
RxCRCSYNC
(Input)
XRT86VX38
42
REV. 1.0.2 OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
AC ELECTRICAL CHARACTERISTICS TRANSMIT FRAMER (HMVIP/H100 MODE)
F
IGURE 5. FRAMER SYSTEM TRANSMIT TIMING DIAGRAM (HMVIP AND H100 MODE)
NOTE: Setup and Hold time is not valid from TxInClk to TxSERCLK as TxInClk is used as the timing source for the back
plane interface and TxSERCLK is used as the timing source on the line side.
Test Conditions: TA = 25°C, VDD = 3.3V +
5% unless otherwise specified
S
YMBOL PARAMETER MIN.TYP.MAX.UNITS CONDITIONS
t
1
TxSYNC Setup Time - HMVIP Mode 7 nS
t
2
TxSYNC Hold Time - HMVIP Mode 4 nS
t
3
TxSYNC Setup Time - H100 Mode 7 nS
t
4
TxSYNC Hold Time - H100 Mode 4 nS
t
5
TxSER Setup Time - HMVIP and H100 Mode 6 nS
t
6
TxSER Hold Time - HMVIP and H100 Mode 3 nS
t
7
TxSIG Setup Time - HMVIP and H100 Mode 6 nS
t
8
TxSIG Hold Time - HMVIP and H100 Mode 3 nS
TxSYNC
(H100 Mode)
TxCHN_0
(TxSIG)
t
4
A
B
CD
t
3
TxSERCLK
TxSER
t
5
t
6
t
7
t
8
TxSYNC
(HMVIP Mode)
t
2
t
1
TxInClk
(16MHz)

XRT86VX38IB329-F

Mfr. #:
Manufacturer:
MaxLinear
Description:
Telecom Interface ICs 8Ch 1.544/2.048Mbps Framer/LIU w/R3 tech
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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