XRT86VX38
51
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. 1.0.2
MICROPROCESSOR INTERFACE I/O TIMING
INTEL INTERFACE TIMING - ASYNCHRONOUS
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR
), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum
external glue logic and is compatible with the timings of the 8051 or 80188 family of microprocessors. The ALE
signal can be tied ’HIGH’ if this signal is not available, and the corresponding timing interface is shown in
Figure 11 and Table 14.
F
IGURE 10. INTEL µP INTERFACE TIMING DURING PROGRAMMED I/O READ AND WRITE OPERATIONS WHEN ALE IS
N
OT TIED ’HIGH’
T
ABLE 13: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS
SYMBOL PARAMETER MIN MAX UNITS
t
0
Valid Address to CS Falling Edge and ALE Rising
Edge
0-ns
t
1
ALE Falling Edge to RD Assert 5 - ns
t
2
RD Assert to RDY Assert - 320 ns
NA RD
Pulse Width (t
2
)320-ns
t
3
ALE Falling Edge to WR Assert 5 - ns
t
4
WR Assert to RDY Assert - 320 ns
NA WR
Pulse Width (t
4
)320-ns
t
5
ALE Pulse Width(t
5
)10 ns
CS
ADDR[14:0]
ALE
DATA[7:0]
RD
WR
RDY
Valid Data for Readback
Data Available to Write Into the LIU
READ OPERATION
WRITE OPERATION
t
0
t
0
t
1
t
4
t
2
t
3
Valid Address
Valid Address
t
5
t
5
