XRT86VX38
19
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. 1.0.3
RxCRCSYNC0
RxCRCSYNC1
RxCRCSYNC2
RxCRCSYNC3
RxCRCSYNC4
RxCRCSYNC5
RxCRCSYNC6
RxCRCSYNC7
D10
D12
A17
C19
V19
W16
V10
R7
A8
C10
C14
E12
R15
R13
R9
N7
O12Receive Multiframe Sync Pulse (RxCRCSYNCn):
The RxCRCSYNCn pins are used to indicate the receive
multi-frame boundary. These pins pulse "High" for one
period of RxSERCLK when the first bit of an inbound
DS1/E1 Multi-frame is being output on the RxCRCSYNCn
pin.
In DS1 ESF mode, RxCRCSYNCn repeats every 3ms
In DS1 SF mode, RxCRCSYNCn repeats every 1.5ms
In E1 mode, RxCRCSYNCn repeats every 2ms.
RxCASYNC0
RxCASYNC1
RxCASYNC2
RxCASYNC3
RxCASYNC4
RxCASYNC5
RxCASYNC6
RxCASYNC7
E10
C14
A16
D19
U17
V15
W10
T9
A9
D11
D13
E13
R14
R12
N9
M8
O12Receive CAS Multiframe Sync Pulse (RxCASYNCn):
- E1 Mode Only
The RxCASYNCn pins are used to indicate the E1 CAS
Multif-frame boundary. These pins pulse "High" for one
period of RxSERCLK when the first bit of an E1 CAS
Multi-frame is being output on the RxCASYNCn pin.
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
D
RIVE (MA)
D
ESCRIPTION
XRT86VX38
20
REV. 1.0.3 OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RxSERCLK0/
RxLINECLK0
RxSERCLK1/
RxLINECLK1
RxSERCLK2/
RxLINECLK2
RxSERCLK3/
RxLINECLK3
RxSERCLK4/
RxLINECLK4
RxSERCLK5/
RxLINECLK5
RxSERCLK6/
RxLINECLK6
RxSERCLK7/
RxLINECLK7
D9
A11
B16
F16
R17
T15
T12
U7
B8
A10
C13
D15
P14
T12
M10
R6
I/O 12 Receive Serial Clock Signal (RxSERCLKn) / Receive
Line Clock (RxLINECLKn):
The exact function of these pins depends on the mode of
operation selected, as described below.
In Base-Rate Mode (1.544MHz/2.048MHz) - RxSER-
CLKn:
These pins are used as the receive serial clock on the
system side interface which can be configured as either
input or output. The receive serial interface outputs data
on RxSERn on the rising edge of RxSERCLKn.
When RxSERCLKn is configured as Input:
These pins will be inputs if the slip buffer on the Receive
path is enabled. System side equipment must provide a
1.544MHz clock rate to this input pin for T1 mode of oper-
ation, and 2.048MHz clock rate in E1 mode.
When RxSERCLKn is configured as Output:
These pins will be outputs if slip buffer is bypassed. The
receive framer will output a 1.544MHz clock rate in T1
mode of operation, and a 2.048MHz clock rate in E1
mode.
DS1/E1 High-Speed Backplane Modes* - (RxSERCLK
as INPUT ONLY)
In this mode, this pin must be used as the high-speed
input clock for the backplane interface to output high-
speed or multiplexed data on the RxSERn pin. The fre-
quency of RxSERCLK is presented in the table below.
N
OTES:
1. *High-speed backplane modes include (For T1/
E1) 2.048MVIP, 4.096MHz, 8.192MHz,
16.384MHz HMVIP, H.100, Bit-multiplexed
modes, and (For T1 only) 12.352MHz Bit-
multiplexed mode.
2. For DS1 high-speed modes, the DS-0 data is
mapped into an E1 frame by ignoring every
fourth time slot (don’t care).
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
D
RIVE (MA)
D
ESCRIPTION
XRT86VX38
21
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. 1.0.3
RxSERCLK0/
RxLINECLK0
RxSERCLK1/
RxLINECLK1
RxSERCLK2/
RxLINECLK2
RxSERCLK3/
RxLINECLK3
RxSERCLK4/
RxLINECLK4
RxSERCLK5/
RxLINECLK5
RxSERCLK6/
RxLINECLK6
RxSERCLK7/
RxLINECLK7
D9
A11
B16
F16
R17
T15
T12
U7
B8
A10
C13
D15
P14
T12
M10
R6
I/O 12 (Continued)
DS1 or E1 Framer Bypass Mode - RxLINECLKn
In this mode, RxSERCLKn is used as the Receive Line
Clock output pin (RxLineClk) from the LIU.
N
OTE: These 8 pins are internally pulled “High” for each
channel.
RxSER0/
RxPOS0
RxSER1/
RxPOS1
RxSER2/
RxPOS2
RxSER3/
RxPOS3
RxSER4/
RxPOS4
RxSER5/
RxPOS5
RxSER6/
RxPOS6
RxSER7/
RxPOS7
D8
C12
B17
B19
V18
V14
W12
V8
B7
B11
B14
B16
P15
P11
T10
P8
O12Receive Serial Data Output (RxSERn):
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Mode - RxSERn
These pins function as the receive serial data output on
the system side interface, which are updated on the rising
edge of the RxSERCLKn pin. All the framing alignment
bits, facility data link bits, CRC bits, and signaling informa-
tion will also be extracted to this output pin.
DS1 or E1 High-Speed Multiplexed Mode* - RxSERn
In this mode, these pins are used as the high-speed multi-
plexed data output pin on the system side. High-speed
multiplexed data of channels 0-3 will output on RxSER0
and high-speed multiplexed data of channels 4-7 will out-
put on RxSER4 in a byte or bit-interleaved way. The
framer outputs the multiplexed data on RxSER0 and
RxSER4 using the high-speed input clock (RxSERCLKn).
DS1 or E1 Framer Bypass Mode
In this mode, RxSERn is used as the positive digital out-
put pin (RxPOSn) from the LIU.
N
OTE: *High-speed multiplexed modes include (For T1/
E1) 16.384MHz HMVIP, H.100, Bit-multiplexed
modes, and (For T1 only) 12.352MHz Bit-
multiplexed mode.
N
OTE: In DS1 high-speed modes, the DS-0 data is
mapped into an E1 frame by ignoring every fourth
time slot (don’t care).
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
D
RIVE (MA)
D
ESCRIPTION

XRT86VX38IB329-F

Mfr. #:
Manufacturer:
MaxLinear
Description:
Telecom Interface ICs 8Ch 1.544/2.048Mbps Framer/LIU w/R3 tech
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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