XRT86VX38
29
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. 1.0.3
RDY/DTACK M16 L16 O 12 Ready/Data Transfer Acknowledge Output:
The exact behavior of this pin depends upon the type of
Microprocessor/Microcontroller the XRT86VX38 has been
configured to operate in, as defined by the PTYPE[2:0]
pins.
Intel Asynchronous Mode - RDY
- Ready Output
Tis output pin will function as the “active-low” READY out-
put.
During a READ or WRITE cycle, the Microprocessor Inter-
face block will toggle this output pin to the logic low level,
ONLY when the Microprocessor Interface is ready to com-
plete or terminate the current READ or WRITE cycle. Once
the Microprocessor has determined that this input pin has
toggled to the logic “low” level, then it is now safe for it to
move on and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor
Interface block is holding this output pin at a logic “high”
level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it detects this output pin being
toggled to the logic low level.
Motorola Asynchronous Mode - DTACK
- Data Transfer
Acknowledge Output
Tis output pin will function as the “active-low” DTACK out-
put.
During a READ or WRITE cycle, the Microprocessor Inter-
face block will toggle this output pin to the logic low level,
ONLY when the Microprocessor Interface is ready to com-
plete or terminate the current READ or WRITE cycle. Once
the Microprocessor has determined that this input pin has
toggled to the logic “low” level, then it is now safe for it to
move on and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor
Interface block is holding this output pin at a logic “high”
level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it detects this output pin being
toggled to the logic low level.
MICROPROCESSOR INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
D
RIVE (MA)
D
ESCRIPTION
