XRT86VX38
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REV. 1.0.2 OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
POWER PC 403 SYCHRONOUS INTERFACE TIMING
The signals used in the Power PC 403 Synchronus microprocessor interface mode are: Address Strobe (AS),
Microprocessor Clock (uPCLK), Data Strobe (DS
), Read/Write Enable (R/W), Chip Select (CS), Address and
Data bits. The interface timing is shown in Figure 13. The I/O specifications are shown in Table 16.
F
IGURE 13. POWER PC 403 INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
TABLE 16: POWER PC 403 MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS
SYMBOL PARAMETER MIN MAX UNITS
t
0
Valid Address to CS Falling Edge 0 - ns
t
1
CS Falling Edge to WE Assert 0 - ns
t
2
WE Assert to TA Assert - 320 ns
NA WE
Pulse Width (t
2
)320-ns
t
3
CS Falling Edge to TS Falling Edge 0 -
t
dc
PCLK Duty Cycle 40 60 %
t
cp
PCLK Clock Period 20 - ns
CS
ADDR[14:0]
DATA[7:0]
WE
R/W
TA
Valid Data for Readback
Data Available to Write Into the LIU
READ OPERATION
WRITE OPERATION
t
0
t
0
Valid Address Valid Address
t
3
t
3
t
1
t
2
TS
uPCLK
t
cp
t
dc
