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MC13203FCR2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
MC13202/203 Technical Data, Rev. 1.1
10 Freescale Semiconductor
5.4 AC Electrical Characteristics
Table 4. Receiver AC Electrical Characteristics
(V
BATT
, V
DDINT
= 2.7 V, T
A
= 25 °C, f
ref
= 16 MHz, unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Sensitivity for 1% Packet Error Rate (PER) (-40 to +85 °C) SENS
per
--92-dBm
Sensitivity for 1% Packet Error Rate (PER) (+25 °C) - -92 -87 dBm
Saturation (maximum input level) SENS
max
-10-dBm
Channel Rejection for 1% PER (desired signal -82 dBm)
+5 MHz (adjacent channel)
-5 MHz (adjacent channel)
+10 MHz (alternate channel)
-10 MHz (alternate channel)
>= 15 MHz
-
-
-
-
-
31
30
43
41
53
-
-
-
-
-
dB
dB
dB
dB
dB
Frequency Error Tolerance - - 200 kHz
Symbol Rate Error Tolerance - - 80 ppm
Table 5. Transmitter AC Electrical Characteristics
(V
BATT
, V
DDINT
= 2.7 V, T
A
= 25 °C, f
ref
= 16 MHz, unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Power Spectral Density (-40 to +85 °C) Absolute limit - -47 - dBm
Power Spectral Density (-40 to +85 °C) Relative limit - 47 -
Nominal Output Power
1
1
SPI Register 12 programmed to 0x00BC which sets output power to nominal (-1 dBm typical).
P
out
-4 -1 2 dBm
Maximum Output Power
2
2
SPI Register 12 programmed to 0x00FF which sets output power to maximum.
4dBm
Error Vector Magnitude EVM - 20 35 %
Output Power Control Range - 30 - dB
Over the Air Data Rate - 250 - kbps
2nd Harmonic - TBD - dBc
3rd Harmonic - TBD - dBc
MC13202/203 Technical Data, Rev. 1.1
Freescale Semiconductor 11
Figure 6 shows a typical AC parameter evaluation circuit.
Figure 6. RF Parametric Evaluation Circuit
Table 6. Digital Timing Specifications
(VBATT, VDDINT = 2.7 V, TA = 25 °C, frequency = 16 MHz, unless otherwise noted.
SPI timing parameters are referenced to Figure 8.
Symbol Parameter Min Typ Max Unit
T0 SPICLK period 125 nS
T1 Pulse width, SPICLK low 50 nS
T2 Pulse width, SPICLK high 50 nS
T3 Delay time, MISO data valid from falling SPICLK 15 nS
T4 Setup time, CE low to rising SPICLK 15 nS
T5 Delay time, MISO valid from CE low 15 nS
T6 Setup time, MOSI valid to rising SPICLK 15 nS
T7 Hold time, MOSI valid from rising SPICLK 15 nS
RST minimum pulse width low (asserted) 250 nS
L2
6.8nH
5
1
6
2
3
4
Z1
LDB212G4005C-001
L3
3. 9 nH
C1
1.0pF
R1
0R
R2
0R
Not Mounted
1
2
5
3
4
J1
SMA_ ed ge_ R ec ep t a
c
C2
10 pF
AN T1
F_Antenna
PAO_M
6
PAO_P
5
RFIN_P
2
RFIN_M
1
CT_Bias
3
U5
MC 13 20 x
L1
1.8nH
L4
1.8nH
MC13202/203 Technical Data, Rev. 1.1
12 Freescale Semiconductor
6 Functional Description
The following sections provide a detailed description of the MC13202/MC13203 functionality including
the operating modes and Serial Peripheral Interface (SPI).
6.1 MC13202/MC13203 Operational Modes
The MC13202/MC13203 has a number of operational modes that allow for low-current operation.
Transition from the Off to Idle mode occurs when RST
is negated. Once in Idle, the SPI is active and is
used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are
summarized, along with the transition times, in Table 7. Current drain in the various modes is listed in
Table 3, DC Electrical Characteristics.
6.2 Serial Peripheral Interface (SPI)
The host microcontroller directs the MC13202/MC13203, checks its status, and reads/writes data to the
device through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction
between the host and the MC13202/MC13203 occurs as multiple 8-bit bursts on the SPI. The SPI signals
are:
1. Chip Enable (CE
) - A transaction on the SPI port is framed by the active low CE input signal. A
transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.
2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13202/MC13203. Data is
clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data
out changes state on the trailing (falling) edge of SPICLK.
NOTE
For Freescale microcontrollers, the SPI clock format is the clock phase
control bit CPHA = 0 and the clock polarity control bit CPOL = 0.
3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.
Table 7. MC13202/MC13203 Mode Definitions and Transition Times
Mode Definition
Transition Time
To or From Idle
Off All IC functions Off, Leakage only. RST asserted. Digital outputs are tri-stated
including IRQ
10 - 25 ms to Idle
Hibernate Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is
retained.
7 - 20 ms to Idle
Doze Crystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 =
1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN
and can
be programmed to enter Idle Mode through an internal timer comparator.
(300 + 1/CLKO) µs to Idle
Idle Crystal Reference Oscillator On with CLKO output available. SPI active.
Receive Crystal Reference Oscillator On. Receiver On. 144 µs from Idle
Transmit Crystal Reference Oscillator On. Transmitter On. 144 µs from Idle
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

MC13203FCR2

Mfr. #:
Buy MC13203FCR2
Manufacturer:
NXP Semiconductors
Description:
IC RF TXRX 802.15.4 32VFQFN
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New from this manufacturer.
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