MC13203FCR2 Datasheet MC13203FC, MC13203FCR2 | P13-P15

MC13202/203 Technical Data, Rev. 1.1

Freescale Semiconductor 13

4. Master In/Slave Out (MISO) - The MC13202/MC13203 presents data to the master on the MISO

output.

A typical interconnection to a microcontroller is shown in Figure 7.

Figure 7. SPI Interface

Although the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock

(CLK

core

), derived from the crystal reference oscillator, to communicate from the SPI registers to internal

registers and memory.

6.2.1 SPI Burst Operation

The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master

(MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the

master on the MISO line. Although an MC13202/MC13203 transaction is three or more SPI bursts long,

the timing of a single SPI burst is shown in Figure 8.

Figure 8. SPI Single Burst Timing Diagram

SPI digital timing specifications are shown in Table 6.

Shift Register

Baud Rate

Generator

Shift Register

Chip Enable (CE)

RxD

MISO

TxD MOSI

Sclk SPICLK

MCU MC13202/203

2345 678

SPICLK

SPI Burst

Valid

MISO

MOSI

Valid

MC13202/203 Technical Data, Rev. 1.1

14 Freescale Semiconductor

6.2.2 SPI Transaction Operation

Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13202/MC13203 requires that

a complete SPI transaction be framed by CE

, and there will be three (3) or more bursts per transaction. The

assertion of CE

to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to

the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and

identifies the access as being a read or write operation. In this context, a write is data written to the

MC13202/MC13203 and a read is data written to the SPI master. The following SPI bursts will be either

the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).

Although the SPI bus is capable of sending data simultaneously between master and slave, the

MC13202/MC13203 never uses this mode. The number of data bytes (payload) will be a minimum of 2

bytes and can extend to a larger number depending on the type of access. The number of payload bytes

sent will always be an even integer. After the final SPI burst, CE

is negated to high to signal the end of the

transaction. Refer to the MC13202/203 Reference Manual, (MC13202RM) for more details on SPI

registers and transaction types.

An example SPI read transaction with a 2-byte payload is shown in Figure 9.

Figure 9. SPI Read Transaction Diagram

SPICLK

MISO

MOSI

Valid

Valid Valid

Clock Burst

Header Read data

MC13202/203 Technical Data, Rev. 1.1

Freescale Semiconductor 15

7 Pin Connections

Table 8. Pin Function Description

Pin # Pin Name Type Description Functionality

1 RFIN_M RF Input RF input/output negative. When used with internal T/R switch, this is

a bi-directional RF port for the internal LNA

and PA

2 RFIN_P RF Input RF input/output positive. When used with internal T/R switch, this is

a bi-directional RF port for the internal LNA

and PA

3 CT_Bias Control voltage Bias voltage/control signal for external

RF components

When used with internal T/R switch,

provides RX ground reference and TX

VDDA reference for use with external

balun. Can also be used as a control signal

for external LNA, PA, or T/R switch.

4 NC Tie to Ground.

5 PAO_P RF Output /DC Input RF Power Amplifier Output Positive. Open drain. Connect to VDDA through a

bias network when used with an external

balun. Not used when internal T/R switch is

used.

6 PAO_M RF Output/DC Input RF Power Amplifier Output Negative. Open drain. Connect to VDDA through a

bias network when used with an external

balun. Not used when internal T/R switch is

used.

7 SM Input Test mode pin. Must be grounded for normal operation.

8 GPIO4

Digital Input/ Output General Purpose Input/Output 4. See Footnote 1

9 GPIO3 Digital Input/ Output General Purpose Input/Output 3.

10 GPIO2 Digital Input/ Output General Purpose Input/Output 2.

When gpio_alt_en, Register 9, Bit 7 =

1, GPIO2 functions as a “CRC Valid”

indicator.

11 GPIO1 Digital Input/ Output General Purpose Input/Output 1.

When gpio_alt_en, Register 9, Bit 7 =

1, GPIO1 functions as an “Out of Idle”

indicator.

12 RST Digital Input Active Low Reset. While held low, the

IC is in Off Mode and all internal

information is lost from RAM and SPI

registers. When high, IC goes to IDLE

Mode, with SPI in default state.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

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