MC13202/203 Technical Data, Rev. 1.1
6 Freescale Semiconductor
4.2 Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon
the baseband energy integrated over a specific time interval. The digital backend performs Differential
Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset
QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.
The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in
RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the
transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured
over a 64 µs period after the packet preamble and stored in RAM.
If the MC13202/MC13203 is in packet mode, the data is processed as an entire packet. The MCU is
notified that an entire packet has been received via an interrupt.
If the MC13202/MC13203 is in streaming mode, the MCU is notified by an interrupt on a word-by-word
basis.
Figure 4 shows CCA reported power level versus input power. Note that CCA reported power saturates at
about -57 dBm input power which is well above 802.15.4 Standard requirements. Figure 5 shows energy
detection/LQI reported level versus input power.
NOTE
For both graphs, the required 802.15.4 Standard accuracy and range limits
are shown. A 3.5 dBm offset has been programmed into the CCA reporting
level to center the level over temperature in the graphs.
Figure 4. Reported Power Level versus Input Power in CCA Mode
-100
-90
-80
-70
-60
-50
-90 -80 -70 -60 -50
Input Power (dBm)
Reported Power Level (dBm)
802.15.4 Accuracy
and range Requirements
