12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
AC ELECTRICAL CHARACTERISTICS
(1)
⎯ SYNCHRONOUS TIMING
(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
Commercial Com’l & Ind’l
(2)
Commercial Commercial
IDT72T1845L4-4 IDT72T1845L5 IDT72T1845L6-7
IDT72T1855L4-4 IDT72T1855L5 IDT72T1855L6-7
IDT72T1865L4-4 IDT72T1865L5 IDT72T1865L6-7
IDT72T1875L4-4 IDT72T1875L5 IDT72T1875L6-7
IDT72T1885L4-4 IDT72T1885L5 IDT72T1885L6-7
IDT72T1895L4-4 IDT72T1895L5 IDT72T1895L6-7
IDT72T18105L4-4 IDT72T18105L5 IDT72T18105L6-7 IDT72T18105L10
IDT72T18115L4-4 IDT72T18115L5 IDT72T18115L6-7 IDT72T18115L10
IDT72T18125L4-4 IDT72T18125L5 IDT72T18125L6-7 IDT72T18125L10
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
fC Clock Cycle Frequency (Synchronous) — 225 — 200 — 150 — 100 MHz
tA Data Access Time 0.6 3.4 0.6 3.6 0.6 3.8 0.6 4.5 ns
tCLK Clock Cycle Time 4.44 — 5 — 6.7 — 10 — ns
tCLKH Clock High Time 2.0 — 2.3 — 2.8 — 4.5 — ns
tCLKL Clock Low Time 2.0 — 2.3 — 2.8 — 4.5 — ns
tDS Data Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tDH Data Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tENS Enable Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tENH Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tLDS Load Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tLDH Load Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tWCSS WCS setup time 1.2 — 1.5 — 2.0 — 3.0 — ns
tWCSH WCS hold time 0.5 — 0.5 — 0.5 — 0.5 — ns
fS Clock Cycle Frequency (SCLK) — 10 — 10 — 10 — 10 MHz
tSCLK Serial Clock Cycle 100 — 100 — 100 — 100 — ns
tSCKH Serial Clock High 45 — 45 — 45 — 45 — ns
tSCKL Serial Clock Low 45 — 45 — 45 — 45 — ns
tSDS Serial Data In Setup 15 — 15 — 15 — 15 — ns
tSDH Serial Data In Hold 5 — 5 — 5 — 5 — ns
tSENS Serial Enable Setup 5 — 5 — 5 — 5 — ns
tSENH Serial Enable Hold 5 — 5 — 5 — 5 — ns
tRS Reset Pulse Width
(3)
30 — 30 — 30 — 30 — ns
tRSS Reset Setup Time 15 — 15 — 15 — 15 — ns
tHRSS HSTL Reset Setup Time 4 — 4 — 4 — 4 — µs
tRSR Reset Recovery Time 10 — 10 — 10 — 10 — ns
tRSF Reset to Flag and Output Time — 10 — 12 — 15 — 15 ns
tWFF Write Clock to FF or IR — 3.4 — 3.6 — 3.8 — 4.5 ns
tREF Read Clock to EF or OR — 3.4 — 3.6 — 3.8 — 4.5 ns
tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 3.4 — 3.6 — 3.8 — 4.5 ns
tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 3.4 — 3.6 — 3.8 — 4.5 ns
tERCLK RCLK to Echo RCLK output — 3.8 — 4 — 4.3 — 5 ns
tCLKEN RCLK to Echo REN output — 3.4 — 3.6 — 3.8 — 4.5 ns
tRCSLZ RCLK to Active from High-Z
(4)
— 3.4 — 3.6 — 3.8 — 4.5 ns
tRCSHZ RCLK to High-Z
(4)
— 3.4 — 3.6 — 3.8 — 4.5 ns
tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR 3.5—4—5—7—ns
t
SKEW2 Skew time between RCLK and WCLK for PAE and PAF 4—5—6—8—ns
