38
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
Figure 14. Write Timing (First Word Fall Through Mode)
NOTES:
1. t
SKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than t
SKEW1, then OR assertion may be delayed one extra RCLK cycle.
2. t
SKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than t
SKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. If x18 input or x18 output bus width is selected, D=2,049 for IDT72T1845, 4,097 for IDT72T1855, 8,193 for IDT72T1865, 16,385 for IDT72T1875, 32,769 for IDT72T1885, 65,537 for IDT72T1895, 131,073 for IDT72T18105, 262,145
for IDT72T18115, 524,288 for IDT72T18125.
If both x9 input and x9 output bus widths are selected, D=4,097 for IDT72T1845, 8,193 for IDT72T1855, 16,385 for IDT72T1865, 32,769 for IDT72T1875, 65,537 for IDT72T1885, 131,073 for IDT72T1895, 262,144 for IDT72T18105,
524,288 for IDT72T18115, 1,048,576 for IDT72T18125.
6. First data word latency = t
SKEW1 + 2*TRCLK + tREF.
W
1
W
2
W
4
W
[n +2]
W
[D-m-1]
W
[D-m-2]
W
[D-1]
W
D
W
[n+3]
W
[n+4]
W
[D-m]
W
[D-m+1]
WCLK
WEN
D0 - Dn
RCLK
t
DH
t
DS
t
SKEW1
(1)
REN
Q0 - Qn
PAF
HF
PAE
IR
t
DS
t
DS
t
DS
t
SKEW2
t
A
t
REF
OR
t
PAES
t
HF
t
PAFS
t
WFF
W
[D-m+2]
W
1
t
ENH
5909 drw18
PREVIOUS DATA IN OUTPUT REGISTER
(2)
W
3
1
2
3
1
D-1
2
+1
][
W
D-1
+2
][
W
2
D-1
+3
][
W
2
1
2
t
ENS
RCS
t
RCSLZ
t
ENS
