40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
Figure 16. Read Cycle and Read Chip Select Timing (First Word Fall Through Mode)
WCLK
12
WEN
D0 - Dn
RCLK
REN
Q0 - Qn
PAF
HF
PAE
IR
OR
W
1
W
2
W
3
W
m+2
W
[m+3]
t
RCSHZ
t
SKEW1
t
ENH
t
DS
t
DH
t
A
t
A
t
PAFS
t
WFF
t
WFF
t
ENS
RCS
t
SKEW2
W
D
5909 drw20
t
PAES
W
[D-n]
W
[D-n-1]
t
A
t
A
W
[D-1]
W
D
t
A
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1)
(2)
t
ENS
1
t
ENS
t
RCSLZ
t
ENS
t
HF
t
REF
D-1
+ 1
][
W
2
D-1
+ 2
][
W
2
t
ENH
NOTES:
1. t
SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than t
SKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. t
SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than t
SKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH.
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. If x18 input or x18 output bus width is selected, D=2,049 for IDT72T1845, 4,097 for IDT72T1855, 8,193 for IDT72T1865, 16,385 for IDT72T1875, 32,769 for IDT72T1885, 65,537 for IDT72T1895, 131,073 for IDT72T18105, 262,145
for IDT72T18115, 524,288 for IDT72T18125.
If both x9 input and x9 output bus widths are selected, D=4,097 for IDT72T1845, 8,193 for IDT72T1855, 16,385 for IDT72T1865, 32,769 for IDT72T1875, 65,537 for IDT72T1885, 131,073 for IDT72T1895, 262,144 for IDT72T18105,
524,288 for IDT72T18115, 1,048,576 for IDT72T18125.
6. OE = LOW.
