16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125 support two different timing modes of opera-
tion: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selection of which mode will operate is determined during Master Reset, by the
state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the FIFO. It also uses the Full Flag function (FF)
to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode, the
first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently depending
on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
(D/2 + 1) words were written into the FIFO. If x18 Input or x18 Output bus Width
is selected, (D/2 + 1) = the 1,025th word for the IDT72T1845, 2,049th word for
IDT72T1855, 4,097th word for the IDT72T1865, 8,193rd word for the
IDT72T1875, 16,385th word for the IDT72T1885, 32,769th word for the
IDT72T1895, 65,537th word for the IDT72T18105, 131,073rd word for the
IDT72T18115 and 262,145th word for the IDT72T18125. If both x9 Input and
x9 Output bus Widths are selected, (D/2 + 1) = the 2,049th word for the
IDT72T1845, 4,097th word for IDT72T1855, 8,193rd word for the IDT72T1865,
16,385th word for the IDT72T1875, 32,769th word for the IDT72T1885,
65,537th word for the IDT72T1895, 131,073rd word for the IDT72T18105,
262,145th word for the IDT72T18115 and 524,289th word for the IDT72T18125.
Continuing to write data into the FIFO will cause the Programmable Almost-Full
flag (PAF) to go LOW. Again, if no reads are performed, the PAF will go LOW
after (D-m) writes to the FIFO. If x18 Input or x18 Output bus Width is selected,
(D-m) = (2,048-m) writes for the IDT72T1845, (4,096-m) writes for the
IDT72T1855, (8,192-m) writes for the IDT72T1865, (16,384-m) writes for the
IDT72T1875, (32,768-m) writes for the IDT72T1885, (65,536-m) writes for the
IDT72T1895, (131,072-m) writes for the IDT72T18105, (262,144-m) writes
for the IDT72T18115 and (524,288-m) writes for the IDT72T18125. If both x9
Input and x9 Output bus Widths are selected, (D-m) = (4,096-m) writes for the
IDT72T1845, (8,192-m) writes for the IDT72T1855, (16,384-m) writes for the
IDT72T1865, (32,768-m) writes for the IDT72T1875, (65,536-m) writes for the
IDT72T1885, (131,072-m) writes for the IDT72T1895, (262,144-m) writes for
the IDT72T18105, (524,288-m) writes for the IDT72T18115 and (1,048,576-m)
writes for the IDT72T18125. The offset “m” is the full offset value. The default
setting for these values are stated in the footnote of Table 2. This parameter is
also user programmable. See section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. If the x18 Input or x18 Output bus Width is selected, D = 2,048 writes
for the IDT72T1845, 4,096 writes for the IDT72T1855, 8,192 writes for the
IDT72T1865, 16,384 writes for the IDT72T1875, 32,768 writes for the
IDT72T1885, 65,536 writes for the IDT72T1895, 131,072 writes for the
IDT72T18105, 262,144 writes for the IDT72T18115 and 524,288 writes for the
IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, D = 4,096
writes for the IDT72T1845, 8,192 writes for the IDT72T1855, 16,384 writes for
the IDT72T1865, 32,768 writes for the IDT72T1875, 65,536 writes for the
IDT72T1885, 131,072 writes for the IDT72T1895, 262,144 writes for the
IDT72T18105, 524,288 writes for the IDT72T18115 and 1,048,576 writes for
the IDT72T18125, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
11, 12, 13 and 18.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into to the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of
Table 2. This parameter is also user programmable. See section on Program-
mable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the (D/2 + 2)
words were written into the FIFO. If x18 Input or x18 Output bus Width is selected,
(D/2 + 2) = the 1,026th word for the IDT72T1845, 2,050th word for IDT72T1855,
4,098th word for the IDT72T1865, 8,194th word for the IDT72T1875, 16,386th
word for the IDT72T1885, 32,770th word for the IDT72T1895, 65,538th word
for the IDT72T18105, 131,074th word for the IDT72T18115 and 262,146th
word for the IDT72T18125. If both x9 Input and x9 Output bus Widths are
selected, (D/2 + 2) = the 2,050th word for the IDT72T1845, 4,098th word for
IDT72T1855, 8,194th word for the IDT72T1865, 16,386th word for the
IDT72T1875, 32,770th word for the IDT72T1885, 65,538th word for the
IDT72T1895, 131,074th word for the IDT72T18105, 262,146th word for the
IDT72T18115 and 524,290th word for the IDT72T18125. Continuing to write
data into the FIFO will cause the PAF to go LOW. Again, if no reads are
performed, the PAF will go LOW after (D-m) writes to the FIFO. If x18 Input or
x18 Output bus Width is selected, (D-m) = (2,049-m) writes for the IDT72T1845,
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, D = 4,097
writes for the IDT72T1845, 8,193 writes for the IDT72T1855, 16,385 writes
for the IDT72T1865, 32,769 writes for the IDT72T1875, 65,537 writes for the
IDT72T1885, 131,073 writes for the IDT72T1895, 262,145 writes for the
IDT72T18105, 524,289 writes for the IDT72T18115 and 1,048,577 writes for
the IDT72T18125, respectively. Note that the additional word in FWFT mode
is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the PAE will go LOW when there are n + 1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is
empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 14, 15,
16 and 19.
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT72T1845/
72T1855/72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/
72T18125 have internal registers for these offsets. There are eight default offset
values selectable during Master Reset. These offset values are shown in Table
2. Offset values can also be programmed into the FIFO in one of two ways; serial
or parallel loading method. The selection of the loading method is done using
the LD (Load) pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled. A HIGH on LD
during Master Reset selects serial loading of offset values. A LOW on LD during
Master Reset selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programming has
been selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125 can be configured during the Master Reset
cycle with either synchronous or asynchronous timing for PAF and PAE flags
by use of the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 23 for synchronous
PAF timing and Figure 24 for synchronous PAE timing.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure 25
for asynchronous PAF timing and Figure 26 for asynchronous PAE timing.
(4,097-m) writes for the IDT72T1855, (8,193-m) writes for the IDT72T1865,
(16,385-m) writes for the IDT72T1875, (32,769-m) writes for the IDT72T1885,
(65,536-m) writes for the IDT72T1895, (131,073-m) writes for the IDT72T18105,
(262,145-m) writes for the IDT72T18115 and (524,289-m) writes for the
IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, (D-m)
= (4,097-m) writes for the IDT72T1845, (8,193-m) writes for the IDT72T1855,
(16,385-m) writes for the IDT72T1865, (32,769-m) writes for the IDT72T1875,
(65,537-m) writes for the IDT72T1885, (131,073-m) writes for the IDT72T1895,
(262,145-m) writes for the IDT72T18105, (524,289-m) writes for the
IDT72T18115 and (1,048,577-m) writes for the IDT72T18125. The offset m
is the full offset value. The default setting for these values are stated in the footnote
of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 2,049
writes for the IDT72T1845, 4,097 writes for the IDT72T1855, 8,193 writes for
the IDT72T1865, 16,385 writes for the IDT72T1875, 32,769 writes for the
IDT72T1885, 65,536 writes for the IDT72T1895, 131,073 writes for the
IDT72T18105, 262,145 writes for the IDT72T18115 and 524,289 writes for the
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
IDT72T1845
Offsets n,m
All Other x9 to x9
*LD FSEL1 FSEL0 Modes Mode
LHL 511 511
L L H 255 255
L L L 127 127
LHH 63 63
H L L 31 1,023
HHL 15 31
HLH 7 15
HHH 3 7
IDT72T1855, 72T1865, 72T1875, 72T1885,
72T1895, 72T18105, 72T18115, 72T18125
*LD FSEL1 FSEL0 Offsets n,m
H L L 1,023
LHL 511
L L H 255
LLL 127
LHH 63
HHL 31
HLH 15
HHH 7
*LD FSEL1 FSEL0 Program Mode
H X X Serial
(3)
L X X Parallel
(4)
*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
0
1 to n
(1)
(n+1) to 1,024
1,025 to (2048-(m+1))
(2048-m)
to 2,047
2,048
0
1 to n
(1)
(n+1) to 2,048
2,049 to (4,096-(m+1))
(4,096-m) to 4,095
4,096
TABLE 3 STATUS FLAGS FOR IDT STANDARD MODE
TABLE 4 STATUS FLAGS FOR FWFT MODE
FF PAF
HF
PAE EF
HH
HL L
HH
HL
H
HH
H
HH
HHL HH
H
L
LHH
LL
LHH
5909 drw05
IR PAF
HF
PAE OR
LH
HL H
LH
HL
L
LH
H
HL
LHLHL
L
L
LHL
HL
LHL
Number of
Words in
FIFO
IW = x18 or
OW = x18
IW = OW = x9
IDT72T18105IDT72T1895 IDT72T18115 IDT72T18125
0
1 to n+1
(1)
(n+2) to 32,769
32,770 to (65,537-(m+1))
(65,537-m) to 65,536
65,537
0
(n+2) to 65,537
65,538 to (131,073-(m+1))
(131,073-m) to 131,072
131,073
0
(n+2) to 131,073
131,074 to (262,145-(m+1))
262,145
(262,145-m) to 262,144
IDT72T18105
IDT72T18115 IDT72T18125
IDT72T1895
IDT72T1885
0
(n+2) to 262,145
262,146 to (524,289-(m+1))
(524,289-m) to 524,288
524,289
0
(n+2) to 524,289
524,290 to (1,048,577-(m+1))
1,048,577
(1,048,577-m) to 1,048,576
1 to n+1
(1)
1 to n+1
(1)
1 to n+1
(1)
1 to n+1
(1)
0
1 to n
(1)
(n+1) to 4,096
4,097 to (8,192-(m+1))
(8,192-m)
to 8,191
8,192
0
1 to n
(
1)
(n+1) to 8,192
8,193 to (16,384-(m+1))
(16,384-m)
to 16,383
16,384
Number of
Words in
FIFO
IDT72T1855
IW = x18 or
OW = x18
IW = OW = x9
IDT72T1855IDT72T1845 IDT72T1865 IDT72T1875
IDT72T1865 IDT72T1875
IDT72T1845
IDT72T1885
0
1 to n
(1)
(n+1) to 16,384
16,385 to (32,768-(m+1))
(32,768-m) to 32,767
32,768
FF PAF
HF
PAE EF
HH
HLL
HH
HL
H
HH
H
HH
HHLHH
H
L
LHH
LL
LHH
Number of
Words in
FIFO
IW = x18 or
OW = x18
IW = OW = x9
IDT72T18105IDT72T1895 IDT72T18115 IDT72T18125
0
1 to n
(1)
(n+1) to 32,768
32,769 to (65,536-(m+1))
(65,536-m) to 65,535
65,536
0
1 to n
(1)
(n+1) to 65,536
65,537 to (131,072-(m+1))
(131,072-m) to 131,071
131,072
0
1 to n
(1)
(n+1) to 131,072
131,073 to (262,144-(m+1))
262,144
(262,144-m) to 262,143
IDT72T18105
IDT72T18115 IDT72T18125
IDT72T1895
IDT72T1885
0
1 to n
(1)
(n+1) to 262,144
262,145 to (524,288-(m+1))
(524,288-m) to 524,287
524,288
0
1 to n
(1)
(n+1) to 524,288
524,289 to (1,048,576-(m+1))
1,048,576
(1,048,576-m) to 1,048,575
0
(n+2) to 1,025
1,026 to (2049-(m+1))
(2049-m)
to 2,048
2,049
0
(n+2) to 2,049
2,050 to (4,097-(m+1))
(4,097-m) to 4,096
4,097
IR PAF
HF
PAE OR
LH
HLH
LH
HL
L
LH
H
HL
LHLHL
L
L
LHL
HL
LHL
0
(n+2) to 4,097
4,098 to (8,193-(m+1))
(8,193-m)
to 8,192
8,193
0
(n+2) to 8,193
8,194 to (16,385-(m+1))
(16,385-m)
to 16,384
16,385
Number of
Words in
FIFO
IDT72T1855
IW = x18 or
OW = x18
IW = OW = x9
IDT72T1855IDT72T1845 IDT72T1865 IDT72T1875
IDT72T1865 IDT72T1875
IDT72T1845
IDT72T1885
0
(n+2) to 16,385
16,386 to (32,769-(m+1))
(32,769-m) to 32,768
32,769
1 to n+1
(1)
1 to n+1
(1)
1 to n+1
(1)
1 to n+1
(1)
1 to n+1
(1)
NOTE:
1. See table 2 for values for n, m.
NOTE:
1. See table 2 for values for n, m.
2. Number of Words in FIFO = Depth + Output Register.

72T1895L4-4BBI

Mfr. #:
Manufacturer:
Description:
IC FIFO 65536X18 4NS 144BGA
Lifecycle:
New from this manufacturer.
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