36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
Figure 11. Write Cycle and Full Flag Timing (IDT Standard Mode)
D
0
- D
n
WEN
RCLK
REN
t
ENH
t
ENH
Q
0
- Q
n
DATA READ
NEXT DATA READ
t
SKEW1
(1)
5909 drw15
WCLK
NO WRITE
1
2
1
2
NO WRITE
t
WFF
t
A
t
ENS
t
ENS
(1)
t
DS
t
A
D
X
t
DH
t
CLK
t
CLKH
FF
RCS
t
ENS
t
RCSLZ
t
WFF
t
SKEW1
t
CLKL
D
X+1
t
WFF
t
WFF
t
DS
t
DH
Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)
5909 drw16
D0 - Dn
t
DS
t
DH
D
0
D
1
t
DS
t
DH
NO OPERATION
RCLK
REN
EF
t
CLK
t
CLKH
t
CLKL
t
ENH
t
REF
t
A
t
OLZ
Q0 - Qn
OE
WCLK
(1)
t
SKEW1
WEN
t
ENS
t
ENS
t
ENH
1
2
t
OLZ
NO OPERATION
LAST WORD
D
0
D
1
t
ENS
t
ENH
t
OHZ
LAST WORD
t
REF
t
ENH
t
ENS
t
A
t
A
t
REF
t
ENS
t
ENH
WCS
t
OE
t
WCSS
t
WCSH
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. RCS is LOW.
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH.
3. WCS = LOW.
