72T1895L4-4BBI Datasheet 72T1865L5BBGI, 72T1865L5BBGI8, 72T1865L5BBI8 | P25-P27

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

2Kx18/4Kx9, 4Kx18/

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

FEBRUARY 10, 2009

OUTPUT ENABLE ( OE )

When Output Enable is enabled (LOW), the parallel output buffers receive

data from the output register. When OE is HIGH, the output data bus (Qn) goes

into a high impedance state. During Master or a Partial Reset the OE is the only

input that can place the output bus Qn, into High-Impedance. During Reset the

RCS input can be HIGH or LOW, it has no effect on the Qn outputs.

READ CHIP SELECT ( RCS )

The Read Chip Select input provides synchronous control of the Read

output port. When RCS goes LOW, the next rising edge of RCLK causes the

Qn outputs to go to the Low-Impedance state. When RCS goes HIGH, the next

RCLK rising edge causes the Qn outputs to return to HIGH Z. During a Master

or Partial Reset the RCS input has no effect on the Qn output bus, OE is the only

input that provides High-Impedance control of the Qn outputs. If OE is LOW the

Qn data outputs will be Low-Impedance regardless of RCS until the first rising

edge of RCLK after a Reset is complete. Then if RCS is HIGH the data outputs

will go to High-Impedance.

The RCS input does not effect the operation of the flags. For example, when

the first word is written to an empty FIFO, the EF will still go from LOW to HIGH

based on a rising edge of RCLK, regardless of the state of the RCS input.

Also, when operating the FIFO in FWFT mode the first word written to an

empty FIFO will still be clocked through to the output register based on RCLK,

regardless of the state of RCS. For this reason the user must take care when

a data word is written to an empty FIFO in FWFT mode. If RCS is disabled when

an empty FIFO is written into, the first word will fall through to the output register,

but will not be available on the Qn outputs which are in HIGH-Z. The user must

take RCS active LOW to access this first word, place the output bus in LOW-Z.

REN must remain disabled HIGH for at least one cycle after RCS has gone LOW.

A rising edge of RCLK with RCS and REN active LOW, will read out the next

word. Care must be taken so as not to lose the first word written to an empty

FIFO when RCS is HIGH. Refer to Figure 17, RCS and REN Read Operation

(FWFT Mode). The RCS pin must also be active (LOW) in order to perform

a Retransmit. See Figure 13 for Read Cycle and Read Chip Select Timing (IDT

Standard Mode). See Figure 16 for Read Cycle and Read Chip Select Timing

(First Word Fall Through Mode).

If Asynchronous operation of the Read port has been selected, then RCS

must be held active, (tied LOW). OE provides three-state control of Qn.

WRITE PORT HSTL SELECT (WHSTL)

The control inputs, data inputs and flag outputs associated with the write port

can be setup to be either HSTL or LVTTL. If WHSTL is HIGH during the Master

Reset, then HSTL operation of the write port will be selected. If WHSTL is LOW

at Master Reset, then LVTTL will be selected.

The inputs and outputs associated with the write port are listed in Table 5.

READ PORT HSTL SELECT (RHSTL)

The control inputs, data inputs and flag outputs associated with the read port

can be setup to be either HSTL or LVTTL. If RHSTL is HIGH during the Master

Reset, then HSTL operation of the read port will be selected. If RHSTL is LOW

at Master Reset, then LVTTL will be selected for the read port, then echo clock

and echo read enable will not be provided.

The inputs and outputs associated with the read port are listed in Table 5.

SYSTEM HSTL SELECT (SHSTL)

All inputs not associated with the write and read port can be setup to be either

HSTL or LVTTL. If SHSTL is HIGH during Master Reset, then HSTL operation

of all the inputs not associated with the write and read port will be selected. If

SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs

associated with SHSTL are listed in Table 5.

LOAD (LD)

This is a dual purpose pin. During Master Reset, the state of the LD input,

along with FSEL0 and FSEL1, determines one of eight default offset values for

the PAE and PAF flags, along with the method by which these offset registers

can be programmed, parallel or serial (see Table 2). After Master Reset, LD

enables write operations to and read operations from the offset registers. Only

the offset loading method currently selected can be used to write to the registers.

Offset registers can be read only in parallel.

After Master Reset, the LD pin is used to activate the programming process

of the flag offset values PAE and PAF. Pulling LD LOW will begin a serial loading

or parallel load or read of these offset values. THIS PIN MUST BE HIGH

AFTER MASTER RESET TO WRITE OR READ DATA TO/FROM THE FIFO

MEMORY.

BUS-MATCHING (IW, OW)

The pins IW and OW are used to define the input and output bus widths.

During Master Reset, the state of these pins is used to configure the device bus

sizes. See Table 1 for control settings. All flags will operate on the word/byte

size boundary as defined by the selection of bus width. See Figure 5 for Bus-

Matching Byte Arrangement.

BIG-ENDIAN/LITTLE-ENDIAN (BE)

During Master Reset, a LOW on BE will select Big-Endian operation. A

HIGH on BE during Master Reset will select Little-Endian format. This function

is useful when data is written into the FIFO in word format (x18) and read out

of the FIFO in word format (x18) or byte format (x9). If Big-Endian mode is

selected, then the most significant byte of the word written into the FIFO will be

read out of the FIFO first, followed by the least significant byte. If Little-Endian

format is selected, then the least significant byte of the word written into the FIFO

will be read out first, followed by the most significant byte. The mode desired

is configured during master reset by the state of the Big-Endian (BE) pin. See

Figure 5 for Bus-Matching Byte Arrangement.

PROGRAMMABLE FLAG MODE (PFM)

During Master Reset, a LOW on PFM will select Asynchronous Program-

mable flag timing mode. A HIGH on PFM will select Synchronous Program-

mable flag timing mode. If asynchronous PAF/PAE configuration is selected

(PFM, LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH

transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of

WCLK. Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of

WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.

If synchronous PAE/PAF configuration is selected (PFM, HIGH during

MRS) , the PAE is asserted and updated on the rising edge of RCLK only and

not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK

only and not RCLK. The mode desired is configured during master reset by

the state of the Programmable Flag Mode (PFM) pin.

INTERSPERSED PARITY (IP)

During Master Reset, a LOW on IP will select Non-Interspersed Parity

mode. A HIGH will select Interspersed Parity mode. The IP bit function allows

the user to select the parity bit in the word loaded into the parallel port (D0-Dn)

when programming the flag offsets. If Interspersed Parity mode is selected, then

the FIFO will assume that the parity bit is located in bit position D8 and D17 during

the parallel programming of the flag offsets, and will therefore ignore D8 when

loading the offset register in parallel mode. This is also applied to the output

selected then output Q8 will be invalid. If Non-Interspersed Parity mode is

selected, then D16 and D17 are the parity bits and are ignored during parallel

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

2Kx18/4Kx9, 4Kx18/

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

FEBRUARY 10, 2009

programming of the offsets. (D8 becomes a valid bit). Additionally, output Q8 will

become a valid bit when performing a read of the offset register. IP mode is

selected during Master Reset by the state of the IP input pin.

OUTPUTS:

FULL FLAG (FF/IR)

This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function

is selected. When the FIFO is full, FF will go LOW, inhibiting further write

operations. When FF is HIGH, the FIFO is not full. If no reads are performed

after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO.

If x18 Input or x18 Output bus Width is selected, D = 2,048 for the IDT72T1845,

4,096 for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the

IDT72T1875, 32,768 for the IDT72T1885, 65,536 for the IDT72T1895,

131,072 writes for the IDT72T18105, 262,144 writes for the IDT72T18115 and

524,288 writes for the IDT72T18125. If both x9 Input and x9 Output bus Widths

are selected, D = 4,096 for the IDT72T1845, 8,192 for the IDT72T1855,

16,384 for the IDT72T1865, 32,768 for the IDT72T1875, 65,536 for the

IDT72T1885, 131,072 for the IDT72T1895, 262,144 writes for the

IDT72T18105, 524,288 writes for the IDT72T18115 and 1,048,576 writes for

the IDT72T18125. See Figure 11, Write Cycle and Full Flag Timing (IDT

Standard Mode), for the relevant timing information.

In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW

when memory space is available for writing in data. When there is no longer

any free space left, IR goes HIGH, inhibiting further write operations. If no reads

are performed after a reset (either MRS or PRS), IR will go HIGH after D writes

to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 2,049 for the

IDT72T1845, 4,097 for the IDT72T1855, 8,193 for the IDT72T1865, 16,385

for the IDT72T1875, 32,769 for the IDT72T1885, 65,537 for the IDT72T1895,

131,073 writes for the IDT72T18105, 262,145 writes for the IDT72T18115 and

524,289 writes for the IDT72T18125. If both x9 Input and x9 Output bus Widths

are selected, D = 4,097 for the IDT72T1845, 8,193 for the IDT72T1855, 16,385

for the IDT72T1865, 32,769 for the IDT72T1875, 65,537 for the IDT72T1885,

131,073 for the IDT72T1895, 262,145 writes for the IDT72T18105, 524,289

writes for the IDT72T18115 and 1,048,577 writes for the IDT72T18125. See

Figure 14, Write Timing (FWFT Mode), for the relevant timing information.

The IR status not only measures the contents of the FIFO memory, but also

counts the presence of a word in the output register. Thus, in FWFT mode, the

total number of writes necessary to deassert IR is one greater than needed to

assert FF in IDT Standard mode.

FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are

double register-buffered outputs.

Note, when the device is in Retransmit mode, this flag is a comparison of the

write pointer to the ‘marked’ location. This differs from normal mode where this

flag is a comparison of the write pointer to the read pointer.

EMPTY FLAG (EF/OR)

This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF)

function is selected. When the FIFO is empty, EF will go LOW, inhibiting further

read operations. When EF is HIGH, the FIFO is not empty. See Figure 12, Read

Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for

the relevant timing information.

In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW

at the same time that the first word written to an empty FIFO appears valid on

the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts the

last word from the FIFO memory to the outputs. OR goes HIGH only with a true

read (RCLK with REN = LOW). The previous data stays at the outputs, indicating

the last word was read. Further data reads are inhibited until OR goes LOW

again. See Figure 15, Read Timing (FWFT Mode), for the relevant timing

information.

EF/OR is synchronous and updated on the rising edge of RCLK.

In IDT Standard mode, EF is a double register-buffered output. In FWFT

mode, OR is a triple register-buffered output.

PROGRAMMABLE ALMOST-FULL FLAG (PAF)

The Programmable Almost-Full flag (PAF) will go LOW when the FIFO

reaches the almost-full condition. In IDT Standard mode, if no reads are

performed after reset (MRS), PAF will go LOW after (D-m) words are written

to the FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (2,048-m)

writes for the IDT72T1845, (4,096-m) writes for the IDT72T1855, (8,192-m)

writes for the IDT72T1865, (16,384-m) writes for the IDT72T1875, (32,768-m)

writes for the IDT72T1885, (65,536-m) writes for the IDT72T1895, (131,072-m)

writes for the IDT72T18105, (262,144-m) writes for the IDT72T18115 and

(524,288-m) writes for the IDT72T18125. If both x9 Input and x9 Output bus

Widths are selected, (D-m) = (4,096-m) writes for the IDT72T1845, (8,192-m)

writes for the IDT72T1855, (16,384-m) writes for the IDT72T1865, (32,768-m)

writes for the IDT72T1875, (65,536-m) writes for the IDT72T1885, (131,072-m)

writes for the IDT72T1895, (262,144-m) writes for the IDT72T18105,

(524,288-m) writes for the IDT72T18115 and (1,048,576-m) writes for the

IDT72T18125. The offset “m” is the full offset value. The default setting for this

value is stated in Table 2.

In FWFT mode, if x18 Input or x18 Output bus Width is selected, the PAF

will go LOW after (2,049-m) writes for the IDT72T1845, (4,097-m) writes for the

IDT72T1855, (8,193-m) writes for the IDT72T1865, (16,385-m) writes for the

IDT72T1875, (32,769-m) writes for the IDT72T1885, (65,537-m) writes for the

IDT72T1895, (131,073-m) writes for the IDT72T18105, (262,145-m) writes

for the IDT72T18115 and (524,289-m) writes for the IDT72T18125. If both x9

Input and x9 Output bus Widths are selected, the PAF will go LOW after (4,097-

m) writes for the IDT72T1845, (8,193-m) writes for the IDT72T1855, (16,385-m)

writes for the IDT72T1865, (32,769-m) writes for the IDT72T1875, (65,537-m)

writes for the IDT72T1885, (131,073-m) writes for the IDT72T1895, (262,145-

m) writes for the IDT72T18105, (524,289-m) writes for the IDT72T18115

and (1,048,577-m) writes for the IDT72T18125. The offset m is the full offset

value. The default setting for this value is stated in Table 2.

See Figure 23, Synchronous Programmable Almost-Full Flag Timing (IDT

Standard and FWFT Mode), for the relevant timing information.

If asynchronous PAF configuration is selected, the PAF is asserted LOW

on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH

on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF

configuration is selected, the PAF is updated on the rising edge of WCLK. See

Figure 25 for Asynchronous Programmable Almost-Full Flag Timing (IDT

Standard and FWFT Mode).

Note, when the device is in Retransmit mode, this flag is a comparison of the

write pointer to the ‘marked’ location. This differs from normal mode where this

flag is a comparison of the write pointer to the read pointer.

PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)

The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO

reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW

when there are n words or less in the FIFO. The offset “n” is the empty offset

value. The default setting for this value is stated in Table 2.

In FWFT mode, the PAE will go LOW when there are n+1 words or less

in the FIFO. The default setting for this value is stated in Table 2.

See Figure 24, Synchronous Programmable Almost-Empty Flag Timing

(IDT Standard and FWFT Mode), for the relevant timing information.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

2Kx18/4Kx9, 4Kx18/

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

FEBRUARY 10, 2009

If asynchronous PAE configuration is selected, the PAE is asserted LOW

on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH

on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE

configuration is selected, the PAE is updated on the rising edge of RCLK. See

Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT

Standard and FWFT Mode), for the relevant timing information.

HALF-FULL FLAG (HF)

This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO

beyond half-full sets HF LOW. The flag remains LOW until the difference

between the write and read pointers becomes less than or equal to half of the

total depth of the device; the rising RCLK edge that accomplishes this condition

sets HF HIGH.

In IDT Standard mode, if no reads are performed after reset (MRS or PRS),

HF will go LOW after (D/2 + 1) writes to the FIFO. If x18 Input or x18 Output

bus Width is selected, D = 2,048 for the IDT72T1845, 4,096 for the IDT72T1855,

8,192 for the IDT72T1865, 16,384 for the IDT72T1875, 32,768 for the

IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105,

262,144 for the IDT72T18115 and 524,288 for the IDT72T18125. If both x9

Input and x9 Output bus Widths are selected, D = 4,096 for the IDT72T1845,

8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the

IDT72T1875, 65,536 for the IDT72T1885, 131,072 for the IDT72T1895,

262,144 for the IDT72T18105, 524,288 for the IDT72T18115 and 1,048,576

for the IDT72T18125.

In FWFT mode, if no reads are performed after reset (MRS or PRS), HF

will go LOW after (D-1/2 + 2) writes to the FIFO. If x18 Input or x18 Output bus

Width is selected, D = 2,049 for the IDT72T1845, 4,097 for the IDT72T1855,

8,193 for the IDT72T1865, 16,385 for the IDT72T1875, 32,769 for the

IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105,

262,145 for the IDT72T18115 and 524,289 for the IDT72T18125. If both x9

Input and x9 Output bus Widths are selected, D = 4,097 for the IDT72T1845,

8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the

IDT72T1875, 65,537 for the IDT72T1885, 131,073 for the IDT72T1895,

262,145 for the IDT72T18105, 524,289 for the IDT72T18115 and 1,048,577

for the IDT72T18125.

See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Mode),

for the relevant timing information. Because HF is updated by both RCLK and

WCLK, it is considered asynchronous.

ECHO READ CLOCK (ERCLK)

The Echo Read Clock output is provided in both HSTL and LVTTL mode,

selectable via RHSTL. The ERCLK is a free-running clock output, it will always

follow the RCLK input regardless of REN, RCS.

The ERCLK output follows the RCLK input with an associated delay. This

delay provides the user with a more effective read clock source when reading

data from the Qn outputs. This is especially helpful at high speeds when

variables within the device may cause changes in the data access times. These

variations in access time maybe caused by ambient temperature, supply

voltage, device characteristics. The ERCLK output also compensates for any

trace length delays between the Qn data outputs and receiving devices inputs.

Any variations effecting the data access time will also have a corresponding

effect on the ERCLK output produced by the FIFO device, therefore the ERCLK

output level transitions should always be at the same position in time relative to

the data outputs. Note, that ERCLK is guaranteed by design to be slower than

the slowest Qn, data output. Refer to Figure 4, Echo Read Clock and Data

Output Relationship, Figure 28, Echo Read Clock & Read Enable Operation

and Figure 29, Echo RCLK & Echo REN Operation for timing information.

ECHO READ ENABLE (EREN)

The Echo Read Enable output is provided in both HSTL and LVTTL mode,

selectable via RHSTL.

The EREN output is provided to be used in conjunction with the ERCLK

output and provides the reading device with a more effective scheme for reading

data from the Qn output port at high speeds. The EREN output is controlled by

internal logic that behaves as follows: The EREN output is active LOW for the

RCLK cycle that a new word is read out of the FIFO. That is, a rising edge of

RCLK will cause EREN to go active, LOW if both REN and RCS are active, LOW

and the FIFO is NOT empty.

SERIAL CLOCK (SCLK)

During serial loading of the programming flag offset registers, a rising edge

on the SCLK input is used to load serial data present on the SI input provided

that the SEN input is LOW.

DATA OUTPUTS (Q0-Qn)

(Q0 - Q17) data outputs for 18-bit wide data or (Q0 - Q8) data outputs for

9-bit wide data.

5909 drw08

ERCLK

SLOWEST

(3)

RCLK

ERCLK

Figure 4. Echo Read Clock and Data Output Relationship

NOTES:

1. REN is LOW;RCS is LOW.

2. tERCLK > tA, guaranteed by design.

3. Qslowest is the data output with the slowest access time, tA.

4. Time, tD is greater than zero, guaranteed by design.

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72T1895L4-4BBI

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