12©2017 Integrated Device Technology, Inc December 18, 2017
5X2503 Datasheet
1
Practical lower frequency is determined by loop filter settings.
2
Includes loading the configuration bits from OTP to PLL registers. It does not include OTP programming/write time.
3
Actual PLL lock time depends on the loop configuration.
I
2
C Bus DC Characteristics
Table 17. AC Timing Electrical Characteristics, 1.2V / 1.8V
V
DD1_8
= 1.8V ±5%, V
DDOUT1
= 1.2V ±5%, V
DDOUT2
= 1.8V ±5%, T
A
= -40°C to +85°C; spread spectrum = off.
Symbol Parameter Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency Single-ended clock output limit (LVCMOS). 1 — 125 MHz
t1 Output Duty Cycle LVCMOS clock < 120MHz. 45 — 55 %
t2 Rise/Fall Time
OUT2/OUT3 LVCMOS output clock rise and fall time, 20%
to 80% of V
DDOUT2
= 1.8V.
—1.01.5ns
OUT1 LVCMOS output clock rise and fall time, 20% to 80%
of V
DDOUT1
= 1.2V.
—1.52.5ns
t3 Clock Jitter
Cycle-to-cycle jitter (peak-to-peak), multiple output
frequencies switching, differential outputs (1.8V nominal
output voltage; 1.2V on V
DDOUT1
).
OUT1 = 25MHz.
OUT2 = 100MHz.
OUT3 = 125MHz.
— 100 350 ps
Cycle-to-cycle jitter (peak-to-peak), multiple output
frequencies switching, differential outputs (1.8V nominal
output voltage; 1.2V on V
DDOUT1
).
OUT1 = 32.768kHz.
OUT2 = 26MHz.
OUT3 = 26MHz.
—50100ps
t5
2
Lock Time PLL lock time from power-up. — 20 ms
t6 Lock Time 32.768kHz clock low-power, power-up time. — 10 100 ms
t6
3
Lock Time PLL lock time from shutdown mode. — 0.1 2 ms
Table 18. I
2
C Bus DC Characteristics
Symbol Parameter Conditions Minimum Typical Maximum Units
V
IH
Input High Level — 0.7 × V
DD1_8
——V
V
IL
Input Low Level — — — 0.3 × V
DD1_8
V
V
HYS
Hysteresis of Inputs — 0.05 × V
DD1_8
——V
I
IN
Input Leakage Current — — — ±1 μA
V
OL
Output Low Voltage I
OL
= 3 mA. — — 0.4 V
