6©2017 Integrated Device Technology, Inc December 18, 2017
5X2503 Datasheet
SCL/SDA are also multiple function pins. The two pins can be configured as output enable control (OE), or I
2
C interface or Dynamic Frequency
Control (DFC) functions by programming and hardware pin latch.
Table 3. OE1 Pin Function Table
Table 4. SDA/SCL Function Selection
Spread Spectrum
The 5X2503 supports spread spectrum clocks from PLL1. PLL1 has built-in analog spread spectrum; PLL2 and PLL3 use seed clock from
PLL1.
ORT – VCO Overshoot Reduction Technology
The 5X2503 supports innovate the VCO overshoot reduction technology to prevent the output clock frequency spike when the device is
change frequency on the fly or doing DFC (Dynamic Frequency Control) function.
The VCO frequency change are under control instead of free run to targeted frequency.
PLL Features and Descriptions
Table 5. Output Divider 1
Function
Byte30
bit6 bit5
OUT1 Output Enable/Disable 0 0
Global Power Down (PD#) 0 1
OUT1 Proactive Power Saving Input (OUT1 PPS) 1 0
DFC0 1 1
SEL_DFC (latched) Enable OE2/3 B36<2> DFC_EN B32<4> OE1 Funsel B30<6:5> Function of SCL/SDA
0 0 0 00, 01, 10 NA
0 0 1 00, 01, 10 SCL = DFC1, SDA = DFC0
0 1 X 00, 01, 10 SCL = OE3, SDA = OE2
1 X X 00, 01, 10 SCL, SDA
Output Divider Bits [1:0]
Output Divider Bits [3:2]
00 01 10 11
00 1248
01 4 8 16 32
10 5 102040
11 6 122448
