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5X2503-000NDGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
22©2017 Integrated Device Technology, Inc December 18, 2017
5X2503 Datasheet
SMBus Table Byte 21: PLL2 Spread Spectrum Control
SMBus Table Byte 22: PLL2 Spread Spectrum Control
SMBus Table Byte 23: PLL2 Period Control
Byte 15h Name Control Function Type 0 1 PWD
Bit 7 PLL2_STEP[15] PLL2 spread step size control bit 15 R/W — — 0
Bit 6 PLL2_STEP[14] PLL2 spread step size control bit 14 R/W — — 0
Bit 5 PLL2_STEP[13] PLL2 spread step size control bit 13 R/W — — 0
Bit 4 PLL2_STEP[12] PLL2 spread step size control bit 12 R/W — — 0
Bit 3 PLL2_STEP[11] PLL2 spread step size control bit 11 R/W — — 0
Bit 2 PLL2_STEP[10] PLL2 spread step size control bit 10 R/W — — 0
Bit 1 PLL2_STEP[9] PLL2 spread step size control bit 9 R/W — — 0
Bit 0 PLL2_STEP[8] PLL2 spread step size control bit 8 R/W — — 0
Byte 16h Name Control Function Type 0 1 PWD
Bit 7 PLL2_STEP_DELTA[7] PLL2 spread step size control delta bit 7 R/W — — 0
Bit 6 PLL2_STEP_DELTA[6] PLL2 spread step size control delta bit 6 R/W — — 0
Bit 5 PLL2_STEP_DELTA[5] PLL2 spread step size control delta bit 5 R/W — — 0
Bit 4 PLL2_STEP_DELTA[4] PLL2 spread step size control delta bit 4 R/W — — 0
Bit 3 PLL2_STEP_DELTA[3] PLL2 spread step size control delta bit 3 R/W — — 0
Bit 2 PLL2_STEP_DELTA[2] PLL2 spread step size control delta bit 2 R/W — — 0
Bit 1 PLL2_STEP_DELTA[1] PLL2 spread step size control delta bit 1 R/W — — 0
Bit 0 PLL2_STEP_DELTA[0] PLL2 spared step size control delta bit 0 R/W — — 0
Byte 17h Name Control Function Type 0 1 PWD
Bit 7 PLL2_PERIOD[7] PLL2 period control bit 7 R/W — — 0
Bit 6 PLL2_PERIOD[6] PLL2 period control bit 6 R/W — — 0
Bit 5 PLL2_PERIOD[5] PLL2 period control bit 5 R/W — — 0
Bit 4 PLL2_PERIOD[4] PLL2 period control bit 4 R/W — — 0
Bit 3 PLL2_PERIOD[3] PLL2 period control bit 3 R/W — — 0
Bit 2 PLL2_PERIOD[2] PLL2 period control bit 2 R/W — — 0
Bit 1 PLL2_PERIOD[1] PLL2 period control bit 1 R/W — — 0
Bit 0 PLL2_PERIOD[0] PLL2 period control bit 0 R/W — — 0
23©2017 Integrated Device Technology, Inc December 18, 2017
5X2503 Datasheet
SMBus Table Byte 24: PLL2 Control Register
SMBus Table Byte 25: PLL2 Charge Pump Control
SMBus Table Byte 26: PLL2 M Divider Setting
Byte 18h Name Control Function Type 0 1 PWD
Bit 7 PLL2_PERIOD[9] PLL2 period control bit 9 R/W — — 0
Bit 6 PLL2_PERIOD[8] PLL2 period control bit 8 R/W — — 0
Bit 5 PLL2_SSEN PLL2 spread spectrum enable R/W disable enable 0
Bit 4 PLL2_R100K PLL2 Loop filter resister 100kΩ R/W bypass plus 100kΩ 0
Bit 3 PLL2_R50K PLL2 Loop filter resister 50kΩ R/W bypass plus 50kΩ 1
Bit 2 PLL2_R25K PLL2 Loop filter resister 25kΩ R/W bypass plus 25kΩ 1
Bit 1 PLL2_R12.5K PLL2 Loop filter resister 12.5kΩ R/W bypass plus 12.5kΩ 1
Bit 0 PLL2_R6K PLL2 Loop filter resister 6kΩ R/W bypass only 6kΩ applied 0
Byte 19h Name Control Function Type 0 1 PWD
Bit 7 PLL2_CP_16X PLL2 charge pump control R/W — x16 0
Bit 6 PLL2_CP_8X PLL2 charge pump control R/W — x8 0
Bit 5 PLL2_CP_4X PLL2 charge pump control R/W — x4 0
Bit 4 PLL2_CP_2X PLL2 charge pump control R/W — x2 1
Bit 3 PLL2_CP_1X PLL2 charge pump control R/W — x1 0
Bit 2 PLL2_CP_/24 PLL2 charge pump control R/W — /24 1
Bit 1 PLL2_CP_/3 PLL2 charge pump control R/W — /3 0
Bit 0 PLL2_SIREF PLL2 SiRef current selection R/W 10μA20μA0
Byte 1Ah Name Control Function Type 0 1 PWD
Bit 7 PLL2_MDIV_Doubler PLL2 reference divider - doubler R/W disable enable 0
Bit 6 PLL2_MDIV1 PLL2 reference divider 1 R/W disable M DIV1 bypadd divider (/1) 0
Bit 5 PLL2_MDIV2 PLL2 reference divider 2 R/W disable M DIV2 bypadd divider (/2) 0
Bit 4 PLL2_MDIV[4] PLL2 reference divider control bit 4 R/W
3–64, default is 26
1
Bit 3 PLL2_MDIV[3] PLL2 reference divider control bit 3 R/W 1
Bit 2 PLL2_MDIV[2] PLL2 reference divider control bit 2 R/W 0
Bit 1 PLL2_MDIV[1] PLL2 reference divider control bit 1 R/W 1
Bit 0 PLL2_MDIV[0] PLL2 reference divider control bit 0 R/W 0
24©2017 Integrated Device Technology, Inc December 18, 2017
5X2503 Datasheet
SMBus Table Byte 27: Output Divider 4
SMBus Table Byte 28: PLL Operation Control Register
SMBus Table Byte 29: Output Control
Byte 1Bh Name Control Function Type 0 1 PWD
Bit 7 OUTDIV3[3] Out divider 4 control bit 7 R/W
DIV3[3:2]=1,2,4,5; DIV3[1:0]=1,3,5,10;
Default divider = 1x5=5
0
Bit 6 OUTDIV3[2] Out divider 4 control bit 6 R/W 0
Bit 5 OUTDIV3[1] Out divider 4 control bit 5 R/W 1
Bit 4 OUTDIV3[0] Out divider 4 control bit 4 R/W 0
Bit 3 OUTDIV4[3] Out divider 4 control bit 3 R/W
DIV4[3:2]=1,2,4,8; DIV4[1:0]=1,3,5,10;
Default divider = 1x10=10
0
Bit 2 OUTDIV4[2] Out divider 4 control bit 2 R/W 0
Bit 1 OUTDIV4[1] Out divider 4 control bit 1 R/W 1
Bit 0 OUTDIV4[0] Out divider 4 control bit 0 R/W 1
Byte 1Ch Name Control Function Type 0 1 PWD
Bit 7 PLL2_HRS_EN PLL2 spread high resolution selection enable R/W normal enable (shift 4 bits) 0
Bit 6 PLL2_refin_sel PLL2 reference clock source select R/W Xtal DIV2 0
Bit 5 PLL3_PDB PLL3 power down R/W power down running 0
Bit 4 PLL3_LCKBYPSSB PLL3 lock bypass R/W bypass lock lock 0
Bit 3 PLL2_PDB PLL2 power down R/W power down running 1
Bit 2 PLL2_LCKBYPSSB PLL2 lock bypass R/W bypass lock lock 1
Bit 1 PLL1_PDB PLL1 power down R/W power down running 0
Bit 0 PLL1_LCKBYPSSB PLL1 lock bypass R/W bypass lock lock 0
Byte 1Dh Name Control Function Type 0 1 PWD
Bit 7
Reserved R/W — — 0
Bit 6
Reserved R/W — — 0
Bit 5 Reserved R/W — — 1
Bit 4 Reserved R/W — — 1
Bit 3
Reserved R/W — — 0
Bit 2 Reserved R/W — — 0
Bit 1
Reserved R/W — — 0
Bit 0 Reserved R/W — — 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

5X2503-000NDGI

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Buy 5X2503-000NDGI
Manufacturer:
IDT
Description:
Clock Generators & Support Products Microclock Programmable Clock Generator
Lifecycle:
New from this manufacturer.
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