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DS2761BE+025

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
DS2761
10 of 24
Figure 7. VOLTAGE REGISTER FORMAT
MSB—Address 0C LSB—Address 0D
S 2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
X X X X X
MSb LSb MSb LSb
Units: 4.88mV
TEMPERATURE MEASUREMENT
The DS2761 uses an integrated temperature sensor to continually measure battery temperature.
Temperature measurements are placed in the temperature register every 220ms in two’s-complement
format with a resolution of 0.125°C over a range of ±127°C. The temperature register format is shown in
Figure 8.
Figure 8. TEMPERATURE REGISTER FORMAT
MSB—Address 18 LSB—Address 19
S 2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
X X X X X
MSb LSb MSb LSb
Units: 0.125°C
PROGRAMMABLE I/O
To use the PIO pin as an output, write the desired output value to the PIO bit in the special feature
register. Writing a 0 to the PIO bit enables the PIO output driver, pulling the PIO pin to V
SS
. Writing a 1
to the PIO bit disables the output driver, allowing the PIO pin to be pulled high or used as an input. To
sense the value on the PIO pin, read the PIO bit. The DS2761 turns off the PIO output driver and sets the
PIO bit high when in sleep mode or when DQ is low for more than 2s, regardless of the state of the
PMOD bit.
POWER SWITCH INPUT
The DS2761 provides a power control function that uses the discharge protection FET to gate battery
power to the system. The
PS
pin, internally pulled to V
DD
through a 1mA current source, is continuously
monitored for a low-impedance connection to V
SS
. If the DS2761 is in sleep mode, the detection of a low
on the
PS
pin causes the device to transition into active mode, turning on the discharge FET. If the
DS2761 is already in active mode, activity on
PS
has no effect other than the latching of its logic low
level in the
PS
bit in the special feature register. The reading of a 0 in the
PS
bit should be immediately
followed by writing a 1 to the
PS
bit to ensure that a subsequent low forced on the
PS
pin is latched into
the
PS
bit.
DS2761
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MEMORY
The DS2761 has a 256-byte linear address space with registers for instrumentation, status, and control in
the lower 32 bytes, with lockable EEPROM and SRAM memory occupying portions of the remaining
address space. All EEPROM and SRAM memory is general purpose except addresses 30h, 31h, and 33h,
which should be written with the default values for the protection register, status register, and current
offset register, respectively. When the MSB of any two-byte register is read, both the MSB and LSB are
latched and held for the duration of the read data command to prevent updates during the read and ensure
synchronization between the two register bytes. For consistent results, always read the MSB and the LSB
of a two-byte register during the same read data command sequence.
EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow
the data to be verified by the host system before being copied to EEPROM. All reads and writes to/from
EEPROM memory actually access the shadow RAM. In unlocked EEPROM blocks, the write data
command updates shadow RAM. In locked EEPROM blocks, the write data command is ignored. The
copy data command copies the contents of shadow RAM to EEPROM in an unlocked block of EEPROM
but has no effect on locked blocks. The recall data command copies the contents of a block of EEPROM
to shadow RAM regardless of whether the block is locked or not.
Table 3. MEMORY MAP
ADDRESS (HEX)
DESCRIPTION
READ/WRITE
00 Protection Register R/W
01 Status Register R
02–06 Reserved
07 EEPROM Register R/W
08 Special Feature Register R/W
09–0B Reserved
0C Voltage Register MSB R
0D Voltage Register LSB R
0E Current Register MSB R
0F Current Register LSB R
10 Accumulated Current Register MSB R/W
11 Accumulated Current Register LSB R/W
12–17 Reserved
18 Temperature Register MSB R
19 Temperature Register LSB R
1A–1F Reserved
20–2F EEPROM, block 0 R/W*
30–3F EEPROM, block 1 R/W*
40–7F Reserved
80–8F SRAM R/W
90–FF Reserved
* Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only.
DS2761
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PROTECTION REGISTER
The protection register consists of flags that indicate protection circuit status and switches that give
conditional control over the charging and discharging paths. Bits OV, UV, COC, and DOC are set when
corresponding protection conditions occur and remain set until cleared by the host system. The default
values of the CE and DE bits of the protection register are stored in lockable EEPROM in the
corresponding bits in address 30h. A recall data command for EEPROM block 1 recalls the default values
into CE and DE. The format of the protection register is shown in Figure 9. The function of each bit is
described in detail in the following paragraphs.
Figure 9. PROTECTION REGISTER FORMAT
Address 00
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OV UV COC DOC
CC
DC
CE DE
OV—Overvoltage Flag. When set to 1, this bit indicates the battery pack has experienced an overvoltage
condition. This bit must be reset by the host system.
UV—Undervoltage Flag. When set to 1, this bit indicates the battery pack has experienced an
undervoltage condition. This bit must be reset by the host system.
COC—Charge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a
charge-direction overcurrent condition. This bit must be reset by the host system.
DOC—Discharge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a
discharge-direction overcurrent condition. This bit must be reset by the host system.
CC — CC Pin Mirror. This read-only bit mirrors the state of the CC output pin.
DC — DC Pin Mirror. This read-only bit mirrors the state of the DC output pin.
CE—Charge Enable. Writing a 0 to this bit disables charging (
CC output high, external charge FET off)
regardless of cell or pack conditions. Writing a 1 to this bit enables charging, subject to override by the
presence of any protection conditions. The DS2761 automatically sets this bit to 1 when it transitions
from sleep mode to active mode.
DE—Discharge Enable. Writing a 0 to this bit disables discharging (
DC output high, external discharge
FET off) regardless of cell or pack conditions. Writing a 1 to this bit enables discharging, subject to
override by the presence of any protection conditions. The DS2761 automatically sets this bit to 1 when it
transitions from sleep mode to active mode.
STATUS REGISTER
The default values for the status register bits are stored in lockable EEPROM in the corresponding bits of
address 31h. A recall data command for EEPROM block 1 recalls the default values into the status
register bits. The format of the status register is shown in Figure 10. The function of each bit is described
in detail in the following paragraphs.
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DS2761BE+025

Mfr. #:
Buy DS2761BE+025
Manufacturer:
Maxim Integrated
Description:
Battery Management
Lifecycle:
New from this manufacturer.
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