DS2761BE+025 Datasheet DS2761BE+025, DS2761AE+, DS2761AE-025 | P4-P6

DS2761

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Table 1. DETAILED PIN DESCRIPTION

SYMBOL TSSOP FLIP

CHIP

DESCRIPTION

1 C1 Charge Protection Control Output. Controls an external p-channel

high-side charge protection FET.

3 B2 Discharge Protection Control Output. Controls an external p-channel

high-side discharge protection FET.

DQ 7 B4 Data Input/Out. 1-Wire data line. Open-drain output driver. Connect

this pin to the DATA terminal of the battery pack. Pin has an internal

1mA pull-down for sensing disconnection.

PIO

14 E2 Programmable I/O Pin. Used to control and monitor user-defined

external circuitry. Open drain to VSS.

PLS 2 B1 Battery Pack Positive Terminal Input. The DS2761 monitors the pack

plus terminal through PLS to detect overcurrent and overload conditions,

as well as the presence of a charge source. Additionally, a charge path to

recover a deeply depleted cell is provided from PLS to V

. In sleep

mode (with SWEN = 0), any capacitance or voltage source connected to

PLS is discharged internally to V

through 200mA (nominal) to assure

reliable detection of a valid charge source. For details of other internal

connections to PLS and associated conditions see the Li+ Protection

Circuitry section.

10 E4 Power Switch Sense Input. The device wakes up from Sleep Mode

when it senses the closure of a switch to VSS on this pin. Pin has an

internal 1mA pull-up to V

VIN 16 D1 Voltage Sense Input. The voltage of the Li+ cell is monitored via this

input pin. This pin has a weak pullup to V

15 E1 Power Supply Input. Connect to the positive terminal of the Li+ cell

through a decoupling network.

VSS

13,14,

F3 Device Ground. Connect directly to the negative terminal of the Li+ cell.

For the external sense resistor configuration, connect the sense resistor

between VSS and SNS.

SNS 4,5,6 A3 Sense Resistor Connection. Connect to the negative terminal of the

battery pack. In the internal sense resistor configuration, the sense resistor

is connected between VSS and SNS.

IS1 9 D4 Current Sense Input. This pin is internally connected to VSS through a

4.7kW resistor. Connect a 0.1m F capacitor between IS1 and IS2 to

complete a low-pass input filter.

IS2 8 C4 Current Sense Input. This pin is internally connected to SNS through a

4.7kW resistor.

SNS

Probe

N/A C2

Do Not Connect.

VSS

Probe

N/A D2

Do Not Connect.

DS2761

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Figure 2. APPLICATION EXAMPLE

1) R

SNS

is present for external sense resistor configurations only.

2) R

SNS-INT

is present for internal sense resistor configurations only.

PLS

SNS

IS2

PIO

IS1

DS2761

104

102 x 2

104

SNS

DS2761

IS2 IS1

4.7KW

voltage

sense

PACK+

PACK-

DAT

150W

150

150W

BAT+

BAT-

SNS

(1)

SNS-INT

(2)

4.7k

DS2761

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POWER MODES

The DS2761 has two power modes: active and sleep. While in active mode, the DS2761 continually

measures current, voltage, and temperature to provide data to the host system and to support current

accumulation and Li+ safety monitoring. In sleep mode, the DS2761 ceases these activities. The DS2761

enters sleep mode when any of the following conditions occurs:

§ The PMOD bit in the Status Register has been set to 1 and the DQ line is low for longer than

2s (pack disconnection)

§ The voltage on V

drops below undervoltage threshold V

for t

UVD

(cell depletion)

§ The pack is disabled through the issuance of a SWAP command (SWEN bit = 1)

The DS2761 returns to active mode when any of the following occurs:

§ The PMOD bit has been set to 1 and the SWEN bit is set to 0 and the DQ line is pulled high

(pack connection)

§ The

pin is pulled low (power switch)

§ The voltage on PLS becomes greater than the voltage on V

(charger connection) with the SWEN bit

set to 0

§ The pack is enabled through the issuance of a SWAP command (SWEN bit = 1)

The DS2761 defaults to sleep mode when power is first applied.

Li+ PROTECTION CIRCUITRY

During active mode, the DS2761 constantly monitors cell voltage and current to protect the battery from

overcharge (overvoltage), overdischarge (undervoltage), and excessive charge and discharge currents

(overcurrent, short circuit). Conditions and DS2761 responses are described in the sections below and

summarized in Table 2 and Figure 3.

Table 2. Li+ PROTECTION CONDITIONS AND DS2761 RESPONSES

ACTIVATION CONDITION

NAME

THRESHOLD DELAY RESPONSE

RELEASE

THRESHOLD

Overvoltage V

> V

OVD CC

high

< V

, or

≤ -2mV

Undervoltage V

< V

UVD CC

high,

Sleep Mode

PLS

> V

(1)

(charger connected)

Overcurrent, Charge V

> V

(2)

OCD CC

high

PLS

< V

- V

(3)

Overcurrent, Discharge V

< -V

(2)

OCD DC

high

PLS

> V

- V

(4)

Short Circuit V

SNS

> V

SCD DC

high

PLS

> V

- V

(4)

= V

IS1

- V

IS2

. Logic high = V

PLS

for

and V

for

All voltages are with respect to V

. I

SNS

references current

delivered from pin SNS.

1) If V

< 2.2V, release is delayed until the recovery charge current (I

) passed from PLS to V

charges the battery and

allows V

to exceed 2.2V.

2) For the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of current: I

SNS

> I

for

charge direction and I

SNS

< -I

for discharge direction

3) With test current I

TST

flowing from PLS to V

(pulldown on PLS)

4) With test current I

TST

flowing from V

to PLS (pullup on PLS)

Overvoltage. If the cell voltage on V

exceeds the overvoltage threshold, V

, for a period longer than

overvoltage delay, t

OVD

, the DS2761 shuts off the external charge FET and sets the OV flag in the

protection register. When the cell voltage falls below charge enable threshold V

, the DS2761 turns the

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DS2761BE+025

Mfr. #:

Buy DS2761BE+025

Manufacturer:

Maxim Integrated

Description:

Battery Management

Lifecycle:

New from this manufacturer.

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DS2761BE+025

DS2761BE+025

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