DS2761BE+025 Datasheet DS2761BE+025, DS2761AE+, DS2761AE-025 | P13-P15

DS2761

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Figure 10. STATUS REGISTER FORMAT

Address 01

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

X X PMOD RNAOP SWEN X X X

PMOD—Sleep Mode Enable. A value of 1 in this bit enables the DS2761 to enter sleep mode when the

DQ line goes low for greater than 2s and to leave sleep mode when the DQ line goes high. A value of 0

disables DQ-related transitions into and out of sleep mode. This bit is read-only. The desired default value

should be set in bit 5 of address 31h. The factory default is 0.

RNAOP—Read Net Address Opcode. A value of 0 in this bit sets the opcode for the read net address

command to 33h, while a 1 sets the opcode to 39h. This bit is read-only. The desired default value should

be set in bit 4 of address 31h. The factory default is 0.

SWEN—SWAP Command Enable. A value of 1 in this bit location enables the recognition of a SWAP

command. If set to 0, SWAP commands are ignored. The desired default value should be set in bit 3 of

address 31h. This bit is read-only. The factory default is 0.

X—Reserved Bits.

EEPROM REGISTER

The format of the EEPROM register is shown in Figure 11. The function of each bit is described in detail

in the following paragraphs.

Figure 11. EEPROM REGISTER FORMAT

Address 07

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

EEC LOCK X X X X BL1 BL0

EEC—EEPROM Copy Flag. A 1 in this read-only bit indicates that a copy data command is in progress.

While this bit is high, writes to EEPROM addresses are ignored. A 0 in this bit indicates that data may be

written to unlocked EEPROM blocks.

LOCK—EEPROM Lock Enable. When this bit is 0, the lock command is ignored. Writing a 1 to this bit

enables the lock command. After the lock command is executed, the LOCK bit is reset to 0. The factory

default is 0.

BL1—EEPROM Block 1 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 1 (addresses

30 to 3F) is locked (read-only) while a 0 indicates block 1 is unlocked (read/write).

BL0—EEPROM Block 0 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 0 (addresses

20 to 2F) is locked (read-only) while a 0 indicates block 0 is unlocked (read/write).

X—Reserved Bits.

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SPECIAL FEATURE REGISTER

The format of the special feature register is shown in Figure 12. The function of each bit is described in

detail in the following paragraphs.

Figure 12. SPECIAL FEATURE REGISTER FORMAT

Address 08

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PIO MSTR X X X X X

PS — PS Pin Latch. This bit latches a low state on the PS pin, and is cleared only by writing a 1 to this

location. Writing this bit to a 1 immediately upon reading of a 0 value is recommended.

PIO—PIO Pin Sense and Control. See the

Programmable I/O section for details on this read/write bit.

MSTR—SWAP Master Status Bit. This bit indicates whether a device has been selected through the

SWAP command. Selection of this device through the SWAP command and the appropriate net address

results in setting this bit, indicating that this device is the master. A 0 signifies that this device is not the

master.

X—Reserved Bits.

1-WIRE BUS SYSTEM

The 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a 1-

Wire bus with multiple slaves. A single-drop bus has only one slave device. In all instances, the DS2761

is a slave device. The bus master is typically a microprocessor in the host system. The discussion of this

bus system consists of four topics: 64-bit net address, hardware configuration, transaction sequence, and

1-Wire signaling.

64-BIT NET ADDRESS

Each DS2761 has a unique, factory-programmed 1-Wire net address that is 64 bits in length. The first

eight bits are the 1-Wire family code (30h for DS2761). The next 48 bits are a unique serial number. The

last eight bits are a cyclic redundancy check (CRC) of the first 56 bits (see Figure 13). The 64-bit net

address and the 1-Wire I/O circuitry built into the device enable the DS2761 to communicate through the

1-Wire protocol detailed in the

1-Wire Bus System section of this data sheet.

Figure 13. 1-WIRE NET ADDRESS FORMAT

8-BIT CRC 48-BIT SERIAL NUMBER 8-BIT FAMILY

CODE (30H)

MSb LSb

CRC GENERATION

The DS2761 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address. To ensure

error-free transmission of the address, the host system can compute a CRC value from the first 56 bits of

the address and compare it to the CRC from the DS2761. The host system is responsible for verifying the

CRC value and taking action as a result. The DS2761 does not compare CRC values and does not prevent

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a command sequence from proceeding as a result of a CRC mismatch. Proper use of the CRC can result

in a communication channel with a very high level of integrity.

The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as

shown in Figure 10, or it can be generated in software. Additional information about the Dallas 1-Wire

CRC is available in Application Note 27,

Understanding and Using Cyclic Redundancy Checks with

Dallas Semiconductor Touch Memory Products. (This application not can be found on the Maxim/Dallas

Semiconductor website at www.maxim-ic.com).

In the circuit in Figure 14, the shift register bits are initialized to 0. Then, starting with the least

significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has

been entered, then the serial number is entered. After the 48th bit of the serial number has been entered,

the shift register contains the CRC value.

Figure 14. 1-WIRE CRC GENERATION BLOCK DIAGRAM

HARDWARE CONFIGURATION

Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive

it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the

bus with open-drain or tri-state output drivers. The DS2761 used an open-drain output driver as part of

the bidirectional interface circuitry shown in Figure 15. If a bidirectional pin is not available on the bus

master, separate output and input pins can be connected together.

The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the

value of this resistor should be approximately 5k

W. The idle state for the 1-Wire bus is high. If, for any

reason, a bus transaction must be suspended, the bus must be left in the idle state in order to properly

resume the transaction later. If the bus is left low for more than 120

ms, slave devices on the bus begin to

interpret the low period as a reset pulse, effectively terminating the transaction.

Figure 15. 1-WIRE BUS INTERFACE CIRCUITRY

1mA

(typ)

100

MOSFET

Rx Rx

Rx = RECEIVE

Tx = TRANSMIT

Vpullup

(2.0V to 5.5V)

4.7kW

BUS MASTER DS2761 1-WIRE PORT

MSb

XOR

LSb

XOR

INPUT

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DS2761BE+025

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DS2761BE+025

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