DS2761
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I/O SIGNALING
The 1-Wire bus requires strict signaling protocols to insure data integrity. The four protocols used by the
DS2761 are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write
1, and read data. All of these types of signaling except the presence pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2761 is shown in Figure 17.
A presence pulse following a reset pulse indicates that the DS2761 is ready to accept a net address
command. The bus master transmits (Tx) a reset pulse for t
RSTL
. The bus master then releases the line and
goes into receive mode (Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After
detecting the rising edge on the DQ pin, the DS2761 waits for t
PDH
and then transmits the presence pulse
for t
PDL
.
Figure 17. 1-WIRE INITIALIZATION SEQUENCE
WRITE-TIME SLOTS
A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level
to a logic-low level. There are two types of write-time slots: write 1 and write 0. All write-time slots must
be t
SLOT
(60ms to 120ms) in duration with a 1ms minimum recovery time, t
REC
, between cycles. The
DS2761 samples the 1-Wire bus line between 15
ms and 60ms after the line falls. If the line is high when
sampled, a write 1 occurs. If the line is low when sampled, a write 0 occurs (see Figure 18). For the bus
master to generate a write 1 time slot, the bus line must be pulled low and then released, allowing the line
to be pulled high within 15
ms after the start of the write time slot. For the host to generate a write 0 time
slot, the bus line must be pulled low and held low for the duration of the write-time slot.
READ-TIME SLOTS
A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a
logic-low level. The bus master must keep the bus line low for at least 1
ms and then release it to allow the
DS2761 to present valid data. The bus master can then sample the data t
RDV
(15ms) from the start of the
read-time slot. By the end of the read-time slot, the DS2761 releases the bus line and allows it to be
pulled high by the external pullup resistor. All read-time slots must be t
SLOT
(60ms to 120ms) in duration
with a 1
ms minimum recovery time, t
REC
, between cycles. See Figure 18 for more information.
t
R
TL
t
PDL
t
R
TH
t
PDH
PACK+
PACK-
LINE TYPE LEGEND:
BOTH BUS MASTER AND
DS2761 ACTIVE LOW
DQ
