DS2761
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SWAP [AAh]. SWAP is a ROM level command specifically intended to aid in distributed multiplexing
applications and is described specifically with regards to power control using the 27xx series of products.
The term power control refers to the ability of the DS2761 to control the flow of power into or out the
battery pack using control pins
DC and CC . The SWAP command is issued followed by the net address.
The effect is to cause the addressed device to enable power to or from the system while simultaneously
(break-before-make) deselecting and powering down (SLEEP) all other packs. This switching sequence is
controlled by a timing pulse issued on the DQ line following the net address. The falling edge of the pulse
is used to disable power with the rising edge enabling power flow by the selected device. The DS2761
recognizes a SWAP command, device address, and timing pulse only if the SWEN bit is set.
FUNCTION COMMANDS
After successfully completing one of the net address commands, the bus master can access the features of
the DS2761 with any of the function commands described in the following paragraphs and summarized in
Table 4. The name of each function is followed by the 8-bit opcode for that command in square brackets.
Read Data [69h, XX]. This command reads data from the DS2761 starting at memory address XX. The
LSb of the data in address XX is available to be read immediately after the MSb of the address has been
entered. Because the address is automatically incremented after the MSb of each byte is received, the LSb
of the data at address XX + 1 is available to be read immediately after the MSb of the data at address XX.
If the bus master continues to read beyond address FFh, the DS2761 outputs logic 1 until a reset pulse
occurs. Addresses labeled “Reserved” in the memory map contain undefined data. The read data
command can be terminated by the bus master with a reset pulse at any bit boundary.
Write Data [6Ch, XX]. This command writes data to the DS2761 starting at memory address XX. The
LSb of the data to be stored at address XX can be written immediately after the MSb of address has been
entered. Because the address is automatically incremented after the MSb of each byte is written, the LSb
to be stored at address XX + 1 can be written immediately after the MSb to be stored at address XX. If
the bus master continues to write beyond address FFh, the DS2761 ignores the data. Writes to read-only
addresses, reserved addresses and locked EEPROM blocks are ignored. Incomplete bytes are not written.
Writes to unlocked EEPROM blocks are to shadow RAM rather than EEPROM. See the
Memory section
for more details.
Copy Data [48h, XX]. This command copies the contents of shadow RAM to EEPROM for the 16-byte
EEPROM block containing address XX. Copy data commands that address locked blocks are ignored.
While the copy data command is executing, the EEC bit in the EEPROM register is set to 1 and writes to
EEPROM addresses are ignored. Reads and writes to non-EEPROM addresses can still occur while the
copy is in progress. The copy data command execution time, t
EEC
, is 2ms typical and starts after the last
address bit is transmitted.
Recall Data [B8h, XX]. This command recalls the contents of the 16-byte EEPROM block containing
address XX to shadow RAM.
Lock [6Ah, XX]. This command locks (write-protects) the 16-byte block of EEPROM memory
containing memory address XX. The LOCK bit in the EEPROM register must be set to l before the lock
command is executed. If the LOCK bit is 0, the lock command has no effect. The lock command is
permanent; a locked block can never be written again.
