74HC_HCT7403 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 24 September 2012 10 of 34
NXP Semiconductors
74HC7403; 74HCT7403
4-bit x 64-word FIFO register; 3-state
t
su
set-up time Dn to SI; see Figure 13
V
CC
= 2.0 V 8 36 - 6-6-ns
V
CC
= 4.5 V 4 13 - 3-3-ns
V
CC
= 6.0 V 3 10 - 3-3-ns
t
h
hold time Dn to SI; see Figure 13
V
CC
= 2.0 V 135 44 - 170 - 205 - ns
V
CC
= 4.5 V 27 16 - 34 - 41 - ns
V
CC
= 6.0 V 23 13 - 29 - 35 - ns
f
max
maximum
frequency
SI, SO burst mode; see
Figure 11 and Figure 12
V
CC
= 2.0 V 3.6 9.9 - 2.8 - 2.4 - MHz
V
CC
= 4.5 V 18 30 - 14 - 12 - MHz
V
CC
=5V; C
L
=15pF - 30 - - - - - MHz
V
CC
= 6.0 V 21 36 - 16 - 14 - MHz
SI, SO
using flags; see
Figure 6 and Figure 9
V
CC
= 2.0 V 3.6 9.9 - 2.8 - 2.4 - MHz
V
CC
= 4.5 V 18 30 - 14 - 12 - MHz
V
CC
=5V; C
L
=15pF - 30 - - - - - MHz
V
CC
= 6.0 V 21 36 - 16 - 14 - MHz
SI, SO
cascaded; see
Figure 6 and Figure 9
V
CC
= 2.0 V - 7.6 - - - - - MHz
V
CC
= 4.5 V - 23 - - - - - MHz
V
CC
= 6.0 V - 27 - - - - - MHz
C
PD
power
dissipation
capacitance
V
I
=GNDtoV
CC
[7]
- 475 - - - - - pF
Table 6. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 17.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC_HCT7403 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 24 September 2012 11 of 34
NXP Semiconductors
74HC7403; 74HCT7403
4-bit x 64-word FIFO register; 3-state
74HCT7403
t
pd
propagation
delay
MR to DIR or DOR; see
Figure 8
[1]
V
CC
= 4.5 V - 30 51 - 53 - 63 ns
SI to DIR; see Figure 6
[1]
V
CC
= 4.5 V - 25 43 - 54 - 65 ns
V
CC
=5V; C
L
=15pF - 17 - - - - - ns
SO
to DOR; see Figure 9
[1]
V
CC
= 4.5 V - 36 61 - 76 - 92 ns
V
CC
=5V; C
L
=15pF - 17 - - - - - ns
DOR to Qn; see Figure 10
[1]
V
CC
= 4.5 V - 7 12 - 15 - 18 ns
SO
to Qn; see Figure 14
[1]
V
CC
= 4.5 V - 42 72 - 90 - 108 ns
t
PHL
HIGH to
LOW
propagation
delay
MR to Qn; see Figure 8
V
CC
= 4.5 V - 22 38 - 48 - 57 ns
t
PLH
LOW to
HIGH
propagation
delay
SI to DOR; see Figure 10
[5]
V
CC
= 4.5 V - 0.8 1.4 - 1.75 - 2.1 s
SO
to DIR; see Figure 7
[6]
V
CC
= 4.5 V - 1.0 1.8 - 2.25 - 2.7 s
t
en
enable time OE to Qn; see Figure 16
[2]
V
CC
= 4.5 V - 16 30 - 38 - 45 ns
t
dis
disable time OE to Qn; see Figure 16
[3]
V
CC
= 4.5 V - 19 30 - 38 - 45 ns
t
t
transition
time
Qn; see Figure 14
[4]
V
CC
= 4.5 V - 5 12 - 15 - 18 ns
t
W
pulse width SI HIGH or LOW;
see Figure 6
V
CC
= 4.5 V 9 5 - 6 - 8 - ns
SO
HIGH or LOW;
see Figure 9
V
CC
= 4.5 V 14 8 - 18 - 21 - ns
DIR HIGH; see Figure 7
V
CC
= 4.5 V 5 17 29 4 36 4 44 ns
DOR HIGH; see Figure 10
V
CC
= 4.5 V 7 21 36 6 45 6 54 ns
MR
LOW; see Figure 8
V
CC
= 4.5 V 26 15 - 33 - 39 - ns
Table 6. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 17.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC_HCT7403 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 24 September 2012 12 of 34
NXP Semiconductors
74HC7403; 74HCT7403
4-bit x 64-word FIFO register; 3-state
[1] t
pd
is the same as t
PLH
and t
PHL
.
[2] t
en
is the same as t
PZH
and t
PZL
.
[3] t
dis
is the same as t
PLZ
and t
PHZ
.
[4] t
t
is the same as t
THL
and t
TLH
.
[5] This is the ripple through delay.
[6] This is the bubble-up delay.
[7] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
t
rec
recovery
time
MR to SI; see Figure 15
V
CC
= 4.5 V 18 10 - 23 - 27 - ns
t
su
set-up time Dn to SI; see Figure 13
V
CC
= 4.5 V 5 16 - 4-4-ns
t
h
hold time Dn to SI; see Figure 13
V
CC
= 4.5 V 30 18 - 38 - 45 - ns
f
max
maximum
frequency
SI, SO burst mode; see
Figure 11
and Figure 12
V
CC
= 4.5 V 18 30 - 14 - 12 - MHz
V
CC
=5V; C
L
=15pF - 30 - - - - - MHz
SI, SO
using flags; see
Figure 6 and Figure 9
V
CC
= 4.5 V 18 30 - 14 - 12 - MHz
V
CC
=5V; C
L
=15pF - 30 - - - - - MHz
SI, SO
cascaded; see
Figure 6
and Figure 9
V
CC
= 4.5 V - 23 - - - - - MHz
C
PD
power
dissipation
capacitance
V
I
=GNDtoV
CC
1.5 V
[7]
- 490 - - - - - pF
Table 6. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 17.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max

74HCT7403D,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC FIFO REGISTER 64X4 3ST 16SOIC
Lifecycle:
New from this manufacturer.
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