74HCT7403D,512 Datasheet 74HCT7403D,512, 74HCT7403D,518, 74HCT7403N,112 | P25-P27

Product data sheet Rev. 4 — 24 September 2012 25 of 34

NXP Semiconductors

74HC7403; 74HCT7403

4-bit x 64-word FIFO register; 3-state

(1) FIFOA and FIFOB are initially empty, SOA held HIGH in anticipation of data

(2) Load one word into FIFOA; SI pulse; applied. results in DIR pulse

(3) Data-out A/ data-in B transition; valid data arrives at FIFOA output stage after a specified delay of the DOR flag, meeting data

input set-up requirements of FIFOB.

(4) DORA and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFOA as a result of the data output

ready pulse, data is shifted into FIFOB

(5) DIRB and SO

A go LOW; flag indicates that input stage of FIFOB is busy, shift-out of FIFOA is complete

(6) DIRB and SO

A go HIGH automatically; the input stage of FIFOB is again able to receive data, SO is held HIGH in anticipation

of additional data

(7) DORB goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFOB output

stage

Fig 22. FIFO to FIFO communication; input timing under empty condition

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Product data sheet Rev. 4 — 24 September 2012 26 of 34

NXP Semiconductors

74HC7403; 74HCT7403

4-bit x 64-word FIFO register; 3-state

(1) FIFOA and FIFOB initially full, SIB held HIGH in anticipation of shifting in new data as an empty location bubbles-up

(2) Unload one word from FIFOB; SO

pulse applied, results in DOR pulse

(3) DIRB and SO

A pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFOB as a result of the DIR pulse, data is

shifted out of FIFOA

(4) DORA and SIB go LOW; flag indicates that the output stage of FIFOA is busy, shift-in of FIFOB is complete

(5) DORA and SIB go HIGH; flag indicates that valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting

bubble-up of empty location.

(6) DIRA goes HIGH; (bubble-up delay after SO

A LOW) an empty location is present at input stage of FIFOA

Fig 23. FIFO to FIFO communication; output timing under full condition

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Product data sheet Rev. 4 — 24 September 2012 27 of 34

NXP Semiconductors

74HC7403; 74HCT7403

4-bit x 64-word FIFO register; 3-state

13.1.1 Sequence 1 (both FIFOs empty, starting SHIFT-IN process)

After an MR pulse has been applied, FIFOA and FIFOB are empty. The DOR flags of

FIFOA and FIFOB go LOW due to no valid data being present at the outputs. The DIR

flags are set HIGH due to the FIFOs being ready to accept data. SO

B is held HIGH and

two SIA pulses are applied (1). These pulses allow two data words to ripple through the

output stage of FIFOA and the input stage of FIFOB (2). When data arrives at the output

of FIFOB, a DORB pulse is generated (3). When SO

B goes LOW, the first bit is shifted out

and a second bit ripples through to the output after which DORB goes high (4).

13.1.2 Sequence 2 (FIFOB runs full)

After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in,

DIRB remains LOW due to FIFOB being full (5). DORA goes LOW due to FIFOA being

empty.

74HCT7403D,512

Mfr. #:

Buy 74HCT7403D,512

Manufacturer:

NXP Semiconductors

Description:

IC FIFO REGISTER 64X4 3ST 16SOIC

Lifecycle:

New from this manufacturer.

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74HCT7403D,512

74HCT7403D,512

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