74HC_HCT7403 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 24 September 2012 14 of 34
NXP Semiconductors
74HC7403; 74HCT7403
4-bit x 64-word FIFO register; 3-state
12.2 With FIFO full; SI held HIGH in anticipation of empty location
Measurement points are given in Table 7.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
(1) FIFO is initially full, shift-in is held HIGH
(2) SO
pulse; data in output stage is unloaded, “bubble-up” process of empty location begins
(3) DIR HIGH; when empty location reaches input stage, flag indicates that FIFO is prepared for data input
(4) DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again
(5) SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full
Fig 7. Bubble-up delay SO input to DIR output, the DIR pulse width.
,1387
9
0
9
0
9
0
W
:
W
3/+
