NXP Semiconductors
74HC7403; 74HCT7403
4-bit x 64-word FIFO register; 3-state
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 September 2012
Document identifier: 74HC_HCT7403
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
19. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 5
7.1 Expanded format . . . . . . . . . . . . . . . . . . . . . . . 5
7.1.1 Parallel expension . . . . . . . . . . . . . . . . . . . . . . 5
7.1.2 Serial expension . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 6
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12.1 Shifting in sequence FIFO empty to FIFO full. 13
12.2 With FIFO full; SI held HIGH in anticipation
of empty location . . . . . . . . . . . . . . . . . . . . . . 14
12.3 Master reset applied with FIFO full. . . . . . . . . 15
12.4 SO
input to DOR output propagation delay . . 16
12.5 With FIFO empty; SO
is held HIGH in
anticipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
12.6 Shift-in operation; high speed burst mode . . . 17
12.7 Shift-out operation; high speed burst mode . . 18
12.8 Set-up and hold times. . . . . . . . . . . . . . . . . . . 18
12.9 SO
input to Qn outputs propagation delay . . . 19
12.10 MR to SI recovery time. . . . . . . . . . . . . . . . . . 19
12.11 Enable and disable times . . . . . . . . . . . . . . . . 20
12.12 Test circuit for measuring switching times . . . 21
13 Application information. . . . . . . . . . . . . . . . . . 22
13.1 Expanded format . . . . . . . . . . . . . . . . . . . . . . 23
13.1.1 Sequence 1 (both FIFOs empty,
starting SHIFT-IN process) . . . . . . . . . . . . . . . 27
13.1.2 Sequence 2 (FIFOB runs full). . . . . . . . . . . . . 27
13.1.3 Sequence 3 (FIFOA runs full). . . . . . . . . . . . . 28
13.1.4 Sequence 4 (both FIFOs full, s
tarting SHIFT-OUT). . . . . . . . . . . . . . . . . . . . . 28
13.1.5 Sequence 5 (FIFOA runs empty) . . . . . . . . . . 28
13.1.6 Sequence 6 (FIFOB runs empty) . . . . . . . . . . 28
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29
15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 31
16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 31
17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 32
17.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 32
17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 32
17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 33
18 Contact information . . . . . . . . . . . . . . . . . . . . 33
19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
