74HC_HCT7403 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 24 September 2012 28 of 34
NXP Semiconductors
74HC7403; 74HCT7403
4-bit x 64-word FIFO register; 3-state
13.1.3 Sequence 3 (FIFOA runs full)
When 65 words are shifted in, DORA remains HIGH due to valid data remaining at the
output of FIFOA. QnA remains HIGH, being the polarity of the 65
th
word (6). After the
128
th
SI pulse, DIR remains LOW and both FIFOs are full (7). Additional pulses have no
effect.
13.1.4 Sequence 4 (both FIFOs full, starting SHIFT-OUT)
SIA is held HIGH and two SOB pulses are applied (8). These pulses shift out two words
and thus allow two empty locations to bubble-up to the input stage of FIFOB, and proceed
to FIFOA (9). When the first empty location arrives at the input of FIFOA, a DIRA pulse is
generated (10) and a new word is shifted into FIFOA. SIA is made LOW and now the
second empty location reaches the input stage of FIFOA, after which DIRA remains HIGH
(11).
13.1.5 Sequence 5 (FIFOA runs empty)
At the start of sequence 5 FIFOA contains 63 valid words due to two words being shifted
out and one word being shifted in, in sequence 4. And additional series of SO
B pulses are
applied. After 63 SO
B pulses, all words from FIFOA are shifted in FIFOB. DORA remains
LOW (12).
13.1.6 Sequence 6 (FIFOB runs empty)
After the next SOB pulse, DIRB remains HIGH due to the input stage of FIFOB being
empty. After another 63 SO
B pulses, DORB remains LOW due to both FIFOS being
empty (14). Additional SO
B pulses have no effect. The last word remains available at the
output Qn.
