74HC_HCT7403 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 24 September 2012 23 of 34
NXP Semiconductors
74HC7403; 74HCT7403
4-bit x 64-word FIFO register; 3-state
13.1 Expanded format
Figure 21 shows two cascaded FIFOs providing a capacity of 128 words x 4 bits.
Figure 22
shows the signals on the nodes of both FIFOs after the application of the SI
pulse, when both FIFOs are initially empty. After a ripple through delay, data arrives at the
output of FIFOA. Due to SO
A being HIGH, a DORA pulse is generated. The requirements
of SIB and DnB are satisfied by the DORA pulse width and the timing between the rising
edge of DORA and QnA. After a second ripple through delay data arrives at the output of
FIFOB.
Figure 23
shows the signals on the nodes of both FIFOs after the application of the SOB
pulse, when both FIFOs are initially full. After a bubble-up delay, a DIRB pulse is
generated, which acts as a SO
A pulse for FIFOA. One word is transferred from the output
of FIFOA to the input of FIFOB. The requirements of the SO
A pulse for FIFOA is satisfied
by the pulse width of DORB. After a second bubble-up delay, an empty space arrives at
DnA, at which time DIRA goes HIGH. Figure 24
shows the waveforms at all external
nodes of both FIFOs during a complete shift-in and shift-out sequence.
This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in cycles are
started or if the SO
output is constantly held HIGH, when the FIFO is full and the automatic shift-out cycles are started (see
Figure 7
and Figure 10).
Fig 20. Expanded FIFO for increased word length
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