OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

1894K-34LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
ICS1894-34
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE 22
ICS1894-34 REV B 052112
17.11 Auto-Negotiation
Progress Monitor Bit 0
Reference Decode Table Reference Decode Table RO LM
X
00
17.10 100Base-TX signal lost Valid signal Signal lost RO LH 0
17.9 100BasePLL Lock Error PLL locked PLL failed to lock RO LH 0
17.8 False Carrier detect Normal Carrier or Idle False Carrier RO LH 0
17.7 Invalid symbol detected Valid symbols observed Invalid symbol received RO LH 0 0
17.6 Halt Symbol detected No Halt Symbol received Halt Symbol received RO LH 0
17.5 Premature End detected Normal data stream Stream contained two
IDLE symbols
RO LH 0
17.4 Auto-Negotiation
complete
Auto-Negotiation in
process
Auto-Negotiation
complete
RO – 0
17.3 100Base-TX signal
detect
Signal present No signal present RO – 1 8
17.2 Jabber detect No jabber detected Jabber detected RO LH 0
17.1 Remote fault No remote fault detected Remote fault detected RO LH 0
17.0 Link Status Link is not valid Link is valid RO LL 0
Register
18 - 10Base-T Operations Register
18.15 Remote Jabber Detect No Remote Jabber
Condition detected
Remote Jabber Condition
Detected
RO LH 0 –
18.14 Polarity reversed Normal polarity Polarity reversed RO LH 0
18.13 Data Bus Mode [1x]=not supported
[01]=SI mode (Serial interface mode)
[00]=MII mode
R0 – –
18.12 R0 – L
18.11 AMDIXEN AMDIX disable AMDIX enable RW – L –
18.10 RXTRI RX output enable RX tri-state for MII
interface
RW – L
18.9 REGEN Vender reserved register
access enable
Vender reserved register
(byte25~byte31) access
disable
RW – L
18.8 TM_SWITCH Switch TMUX2 to TMUX1, test control RW – 0
18.7 ICS reserved Reserved Reserved RW/0 – – –
18.6 ICS reserved Reserved Reserved RW/0 – –
18.5 Jabber inhibit Normal Jabber behavior Jabber Check disabled RW – 0
18.4 ICS reserved Reserved Reserved RW/1 – 1
18.3 Auto polarity inhibit Polarity automatically
corrected
Polarity not automatically
corrected
RW – 0 0
18.2 SQE test inhibit Normal SQE test
behavior
SQE test disabled RW – 0
18.1 Link Loss inhibit Normal Link Loss
behavior
Link Always = Link Pass RW – 0
18.0 Squelch inhibit Normal squelch behavior No squelch RW – 0
Bit Definition When Bit = 0 When Bit = 1 Access
2
SF
2
Default
3
Hex
ICS1894-34
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE 23
ICS1894-34 REV B 052112
Register 19 - Extended Control Register
19.15 Node Mode Node mode Repeater mode (mode not
supported)
RW – L –
19.14 Hardware/Software
Mode Speed Select
Use bit00.13 to select
speed
Use real time input pin 22
only to select speed
RW – L
19.13 Remote Fault No faults detected Remote fault detected RO – 0
19.12 Register Bank select [01]=Bank1, access register0x00~0x13 and
ICS1893CF registers 0x14~0x1F
[00]=Bank0, access register0x00~0x13, new defined
registers 0x14~0x25
[1x]=Bank0, same as [00]
RW – 0
19.11 RW – 0 2
19.10 ICS reserved Reserved Reserved RO – 0
19.9 AMDIX_EN See Table on page 11 See Table on page 11 RW – 1
19.8 MDI_MODE See Table on page 11 See Table on page 11 RW – 0
19.7 Twisted Pair Tri-State
Enable, TPTRI
Twisted Pair Signals are
not Tri-Stated or No
effect
Twisted Pair Signals are
Tri-Stated
RW – 0 0
19.6 ICS reserved Reserved Reserved RW – 0
19.5 ICS reserved Reserved Reserved RW – 0
19.4 ICS reserved Reserved Reserved RW – 0
19.3 ICS reserved Reserved Reserved RW – 0 1
19.2 ICS reserved Reserved Reserved RW – 0
19.1 ICS reserved Reserved Reserved RW – 0
19.0 Automatic 100Base-TX
Power Down
Do not automatically
power down
Power down automatically RW – 1
Register
20 - Extended Control Register
20.15 Str_enhance Normal digital output
strength
Enhance digital output
strength in 1.8V condition
RW 0
3
20.14 ICS reserved Reserved Reserved RW – 0
20.13 ICS reserved Reserved Reserved RW – 1
20.12 1
Bit Definition When Bit = 0 When Bit = 1 Access
2
SF
2
Default
3
Hex
ICS1894-34
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE 24
ICS1894-34 REV B 052112
20.11 ICS reserved Reserved Reserved RW – 1
F
20.10 1
20.9 1
20.8
ICS reserved
Reserved Reserved RW – 1
20.7 1
E
20.6 1
20.5 LED1 Mode 000 = Link Integrity
001 = activity/no activity
010 = Transmit Data
011 = Receive Data
100 = Collision
101 = 100/10 mode (Default LED1)
110 = Full Duplex
111 = OFF
RW 1
20.4 0
20.3 1
9
20.2 LED0 Mode 000 = Link Integrity
001 = activity/no activity (Default LED0)
010 = Transmit Data
011 = Receive Data
100 = Collision
101 = 100/10 mode
110 = Full Duplex
111 = LINK_STAT
RW 0
20.1 0
20.0 1
Register
21 - Extended Control Register
21.15:0
ICS reserved
Reserved RW –
0
Register 22 - Extended Control Register
22.15 Interrupt output enable Disable interrupt output Enable interrupt output RW 0
0
22.14 Interrupt flag read clear
enable
Interrupt flag clear by
read disable
Interrupt flag clear by read
enable
RW 0
22.13 Interrupt polarity Output low when
interrupt occur
Output high when
interrupt occur
RW 0
22.12 Interrupt flag auto clear
enable
Interrupt flag unchanged
when interrupt condition
removed
Interrupt flag cleared
when interrupt condition
removed
RW 0
22.11 Interrupt flag re-setup
enable
Interrupt flag always
cleared when write 1 to
flag bit
Interrupt flag remains
unchanged when
interrupt condition exists
when a 1 is written to flag
bit.
RW 0
0
22.10 Interrupt Enable Disable Deep power
down wake up Interrupt
Enable Deep power down
wake up Interrupt
RW 0
22.9 Interrupt Enable Disable Deep power
down Interrupt
Enable Deep power down
Interrupt
RW 0
22.8 Interrupt Enable Disable Auto-Negotiation
Complete Interrupt
Enable Auto-Negotiation
Complete Interrupt
RW 0
Bit Definition When Bit = 0 When Bit = 1 Access
2
SF
2
Default
3
Hex
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

1894K-34LFT

Mfr. #:
Buy 1894K-34LFT
Manufacturer:
IDT
Description:
Ethernet ICs 3.3V 10/100 PHY RMII
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet