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1894K-34LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
ICS1894-34
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE 40
ICS1894-34 REV B 052112
10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
The table below lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex
transmission. The time periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• CRS
The 10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) shows the timing diagram for
the time periods.
10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 TXEN Asserted to CRS Assert 0 – 2 Bit times
t2 TXEN De-Asserted to CRS De-Asserted 0 2 4 Bit times
ICS1894-34
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE 41
ICS1894-34 REV B 052112
100M MII Media Independent Interface: Receive Latency
The table below lists the significant time periods for the 100M MII/100M Stream Interface receive latency. The time
periods consist of timings of signals on the following pins:
• TP_RX (that is, TP_RXP and TP_RXN)
• RXCLK
• RXD (that is, RXD[3:0])
The 100M MII/100M Stream Interface: Receive Latency Timing Diagram shows the timing diagram for the time
periods.
100M MII/100M Stream Interface: Receive Latency Timing Diagram
Reset: Power-On Reset
The table below lists the significant time periods for the power-on reset. The time periods consist of timings of
signals on the following pins:
• VDD
• TXCLK
The Power-On Reset Timing Diagram shows the timing diagram for the time periods.
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 First Bit of /J/ into TP_RX to /J/ on RXD 100M MII – 16 17 Bit times
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 VDD ≥ 2.7 V to Reset Complete – 40 45 500 ms
ICS1894-34
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE 42
ICS1894-34 REV B 052112
Power-On Reset Timing Diagram
Reset: Hardware Reset and Power-Down
The table below lists the significant time periods for the hardware reset and power-down reset. The time periods
consist of timings of signals on the following pins:
• REFIN
• RESETn
• TXCLK
The Hardware Reset and Power-Down Timing Diagram shows the timing diagram for the time periods.
Hardware Reset and Power-Down Timing Diagram
Time
Period
Parameter Conditions Min. Typ. Max
.
Units
t1 RESETn Active to Device Isolation and Initialization – – 60 – ns
t2 Minimum RESETn Pulse Width – 200 – ns
t3 RESETn Released to TXCLK Valid – – 35 500 ms
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

1894K-34LFT

Mfr. #:
Buy 1894K-34LFT
Manufacturer:
IDT
Description:
Ethernet ICs 3.3V 10/100 PHY RMII
Lifecycle:
New from this manufacturer.
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