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1894K-34LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
ICS1894-34
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE 34
ICS1894-34 REV B 052112
100M MII: Synchronous Transmit Timing
The table below lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time
periods consist of timings of signals on the following pins:
• TXCLK
• TXD[3:0]
• TXEN
• TXER
The 100M MII/100M Stream Interface Synchronous Transmit Timing Diagram figure shows the timing diagram for
the time periods.
100M MII/100M Stream Interface Synchronous Transmit Timing Diagram
10M MII: Synchronous Transmit Timing
The table below lists the significant time periods for the 10M MII synchronous transmit timing. The time periods
consist of timings of signals on the following pins:
• TXCLK
• TXD[3:0]
• TXEN
• TXER
The 10M MII Synchronous Transmit Timing Diagram figure shows the timing diagram for the time periods.
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 TXD[3:0], TXEN, TXER Setup to TXCLK Rise – 15 – – ns
t2 TXD[3:0], TXEN, TXER Hold after TXCLK Rise – 0 – – ns
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 TXD[3:0], TXEN, TXER Setup to TXCLK Rise – 375 – – ns
t2 TXD[3:0], TXEN, TXER Hold after TXCLK Rise – 0 – – ns
ICS1894-34
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE 35
ICS1894-34 REV B 052112
10M MII Synchronous Transmit Timing Diagram
100M/MII Media Independent Interface: Synchronous Receive Timing
The table below lists the significant time periods for the MII/100M Stream Interface synchronous receive timing. The
time periods consist of timings of signals on the following pins:
• RXCLK
• RXD[3:0]
• RXDV
• RXER
The MII Interface: Synchronous Receive Timing figure shows the timing diagram for the time periods.
MII Interface: Synchronous Receive Timing
Time
Period
Parameter Min. Typ. Max. Units
t1 RXD[3:0], RXDV, and RXER Setup to RXCLK Rise 10.0 – – ns
t2 RXD[3:0], RXDV, and RXER Hold after RXCLK Rise 10.0 – – ns
ICS1894-34
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE 36
ICS1894-34 REV B 052112
MII Management Interface Timing
The table below lists the significant time periods for the MII Management Interface timing (which consists of timings
of signals on the MDC and MDIO pins). The MII Management Interface Timing Diagram figure shows the timing
diagram for the time periods.
MII Management Interface Timing Diagram
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 MDC Minimum High Time – 160 – – ns
t2 MDC Minimum Low Time – 160 – – ns
t3 MDC Period – 400 – – ns
t4 MDC Rise Time to MDIO Valid – 0 – 300 ns
t5 MDIO Setup Time to MDC – 10 – – ns
t6 MDIO Hold Time after MDC – 10 – – ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

1894K-34LFT

Mfr. #:
Buy 1894K-34LFT
Manufacturer:
IDT
Description:
Ethernet ICs 3.3V 10/100 PHY RMII
Lifecycle:
New from this manufacturer.
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