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1894K-34LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
ICS1894-34
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE 31
ICS1894-34 REV B 052112
DC Operating Characteristics for Inputs and Outputs
Unless otherwise specified, the table below lists the 3.3V/1.8 V DC operating characteristics of the ICS1894-34
inputs and outputs.
For 3.3 V Signals
For 1.8 V Signals
Parameter Symbol Conditions Min. Max. Units
Input High Voltage V
IH
2.0 – V
Input Low Voltage V
IL
–0.8V
Output High Voltage V
OH
I
OH
= –4 mA 2.4 – V
Output Low Voltage V
OL
I
OL
= +4 mA – 0.4 V
Parameter Symbol Conditions Min. Max. Units
Input High Voltage V
IH
0.8 – V
Input Low Voltage V
IL
–0.7V
Output High Voltage V
OH
I
OH
= –4 mA 1.6 – V
Output Low Voltage V
OL
I
OL
= +4 mA – 0.1 V
ICS1894-34
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE 32
ICS1894-34 REV B 052112
DC Operating Characteristics for REFIN
The table below lists the 3.3V DC characteristics for the REFIN pin.
DC Operating Characteristics for MII Pins
The table below lists DC operating characteristics for the Media Independent Interface (MII) for the ICS1894-34.
Timing Diagrams
Timing for Clock Reference (REFIN) Pin
The table below lists the significant time periods for signals on the clock reference (REFIN) pin. The REFIN Timing
Diagram figure shows the timing diagram for the time periods.
REFIN Timing Diagram
Parameter Symbol Min. Max. Units
Input High Voltage V
IH
2.97 – V
Input Low Voltage V
IL
–0.33 V
Parameter Conditions Min. Typ. Max. Units
MII Input Pin Capacitance – – – 8 pF
MII Output Pin Capacitance – – – 14 pF
MII Output Drive Impedance VDDIO = 3.3V – 20 – Ω
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 REFIN Duty Cycle (MII) – 45 50 55 %
t2 REFIN Period (MII) – – 40 – ns
ICS1894-34
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE 33
ICS1894-34 REV B 052112
Timing for Transmit Clock (TXCLK) Pin
The table below lists the significant time periods for signals on the Transmit Clock (TXCLK) pin. The Transmit Clock
Timing Diagram figure shows the timing diagram for the time periods.
Transmit Clock Timing Diagram
Timing for Receive Clock (RXCLK) Pin
The table below lists the significant time periods for signals on the Receive Clock (RXCLK) pin. The Receive Clock
Timing Diagram figure shows the timing diagram for the time periods.
Receive Clock Timing Diagram
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 TXCLK Duty Cycle – 35 50 65 %
t2a TXCLK Period 100M MII (100Base-TX) – 40 – ns
t2b TXCLK Period 10M MII (10Base-T) – 400 – ns
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 RXCLK Duty Cycle – 35 50 65 %
t2a RXCLK Period 100M MII (100Base-TX) – 40 – ns
t2b RXCLK Period 10M MII (10Base-T) – 400 – ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

1894K-34LFT

Mfr. #:
Buy 1894K-34LFT
Manufacturer:
IDT
Description:
Ethernet ICs 3.3V 10/100 PHY RMII
Lifecycle:
New from this manufacturer.
Delivery:
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