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SST39VF3201C-70-4I-B3KE

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
©2014 Silicon Storage Technology, Inc. DS20005020B 07/14
10
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
Data# Polling (DQ
7
)
When the SST39VF3201C/3202C are in the internal Program operation, any attempt to read DQ
7
will
produce the complement of the true data. Once the Program operation is completed, DQ
7
will produce
true data. Note that even though DQ
7
may have valid data immediately following the completion of an internal
Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in
subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt
to read DQ
7
will produce a ‘0’. Once the internal Erase operation is completed, DQ
7
will produce a ‘1’.
The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 8 for Data# Polling timing diagram and Figure 22 for a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ
6
will produce
alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation
is completed, the DQ
6
bit will stop toggling. The device is then ready for the next operation. For Sector-
, Block-, or Chip-Erase, the toggle bit (DQ
6
) is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ
6
will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro-
gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ
6
will toggle.
An additional Toggle Bit is available on DQ
2
, which can be used in conjunction with DQ
6
to check
whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status
bits information. The Toggle Bit (DQ
2
) is valid after the rising edge of the last WE# (or CE#) pulse of
Write operation. See Figure 9 for Toggle Bit timing diagram and Figure 22 for a flowchart.
Note: DQ
7
,DQ
6
and DQ
2
require a valid address when reading status information.
Table 3: Write Operation Status
Status
DQ
7
DQ
6
DQ
2
R Y/BY#
Normal Operation Standard Program DQ
7
# Toggle No
Toggle
0
Standard Erase 0 Toggle Toggle 0
Erase-Suspend
Mode
Read from Erase-Sus-
pended Sector/Block
1 1 Toggle 1
Read from Non- Erase-
Suspended Sector/Block
Data Data Data 1
Program DQ
7
# Toggle N/A 0
T3.0 20005020
©2014 Silicon Storage Technology, Inc. DS20005020B 07/14
11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that
indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain out-
put, it allows several devices to be tied in parallel to V
DD
via an external pull-up resistor. After the rising
edge of the final WE# pulse in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress.
When RY/BY# is high (Ready), the devices may be read or left in standby mode.
Data Protection
The SST39VF3201C/3202C provide both hardware and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-down.
Hardware Block Protection
The SST39VF3202C support top hardware block protection, which protects the top two 4-KWord
blocks of the device. The SST39VF3201C support bottom hardware block protection, which protects
the bottom two 4-KWord blocks of the device. The Boot Block address ranges are described in Table 4.
Program and Erase operations are prevented on the two 4-KWord blocks when WP# is low. If WP# is
left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling
Program and Erase operations on that block.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the device to read array data. When the RST#
pin is held low for at least T
RP,
any in-progress operation will terminate and return to Read mode. When
no internal Program/Erase operation is in progress, a minimum period of T
RHR
is required after RST#
is driven high before a valid Read can take place. See Figure 17.
The Erase or Program operation that has been interrupted needs to be re-initiated after the device
resumes normal operation mode to ensure data integrity.
Table 4: Boot Block Address Ranges
Product Address Range
Bottom Boot Block
SST39VF3201C 000000H-001FFFH
Top Boot Block
SST39VF3202C 1FE000H-1FFFFFH
T4.0 20005020
©2014 Silicon Storage Technology, Inc. DS20005020B 07/14
12
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
Software Data Protection (SDP)
The SST39VF3201C/3202C provide the JEDEC approved Software Data Protection scheme for all data
alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the
three-byte sequence. The three-byte load sequence is used to initiate the Program operation, provid-
ing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-
down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped
with the Software Data Protection permanently enabled. See Table 7 for the specific software com-
mand codes. During SDP command sequence, invalid commands will abort the device to read mode
within T
RC.
The contents of DQ
15
-DQ
8
can be V
IL
or V
IH
, but no other value, during any SDP command
sequence.
Common Flash Memory Interface (CFI)
The SST39VF3201C/3202C also contain the CFI information to describe the characteristics of the
device. In order to enter the CFI Query mode, the system must write the three-byte sequence, same as
product ID entry command with 98H (CFI Query command) to address 555H in the last byte sequence.
The system can also enter the CFI Query mode, by using the one-byte sequence with 55H on Address
and 98H on Data Bus. Once the device enters the CFI Query mode, the system can read CFI data at
the addresses given in Tables 8 through 10. The system must write the CFI Exit command to return to
Read mode from the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices as the SST39VF3201Cand SST39VF3202C, and
the manufacturer as Microchip. This mode may be accessed through software operations. Users may
use the Software Product Identification operation to identify the part (i.e., using the device ID) when
using multiple manufacturers in the same socket. For details, see Table 7 for software operation, Figure
13 for the Software ID Entry and Read timing diagram and Figure 23 for the Software ID Entry com-
mand sequence flowchart.
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to
the Read mode. This command may also be used to reset the device to the Read mode after any inad-
vertent transient condition that apparently causes the device to behave abnormally, e.g., not read cor-
rectly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program
or Erase operation. See Table 7 for software command codes, Figure 15 for timing waveform, and Fig-
ure 23 and Figure 24 for flowcharts.
Table 5: Product Identification
Address Data
Manufacturer’s ID 0000H BFH
Device ID
SST39VF3201C 0001H 235F
SST39VF3202C 0001H 235E
T5.0 20005020
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

SST39VF3201C-70-4I-B3KE

Mfr. #:
Buy SST39VF3201C-70-4I-B3KE
Manufacturer:
Microchip Technology
Description:
NOR Flash 2.7V to 3.6V 32Mbit Multi-Prps Fl
Lifecycle:
New from this manufacturer.
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